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Searched refs:GPR64 (Results 1 – 16 of 16) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td184 (STLRX GPR64:$val, GPR64sp:$ptr)>;
192 (STRXroX GPR64:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
293 def : Pat<(stxr_1 GPR64:$val, GPR64sp:$addr),
295 def : Pat<(stxr_2 GPR64:$val, GPR64sp:$addr),
297 def : Pat<(stxr_4 GPR64:$val, GPR64sp:$addr),
299 def : Pat<(stxr_8 GPR64:$val, GPR64sp:$addr),
300 (STXRX GPR64:$val, GPR64sp:$addr)>;
396 (ins GPR64:$addr, GPR64:$desired, GPR64:$new), []>,
402 def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch),
403 (ins GPR64:$addr, GPR64:$desiredLo, GPR64:$desiredHi,
[all …]
H A DAArch64InstrInfo.td983 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
984 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
1044 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;
1046 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;
1070 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
1071 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
1076 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
1381 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
1561 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1566 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
[all …]
H A DAArch64InstrFormats.td1662 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
1664 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1853 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1854 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1863 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1870 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1872 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1894 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
2201 GPR64, GPR64, GPR64, 0>;
2298 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
[all …]
H A DAArch64RegisterInfo.td138 // GPR64/GPR64sp for use by the coalescer.
154 let AltOrders = [(rotl GPR64, 8)];
182 // GPR32/GPR64 but with zero-register substitution enabled.
183 // TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all.
187 def GPR64z : RegisterOperand<GPR64> {
216 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
217 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
218 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
219 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
220 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
[all …]
H A DSVEInstrFormats.td436 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
525 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
826 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
1461 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
2263 def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>;
2264 def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>;
2446 def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
2470 def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
2494 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
3167 def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>;
[all …]
H A DAArch64SVEInstrInfo.td769 def CTERMEQ_XX : sve_int_cterm<0b1, 0b0, "ctermeq", GPR64>;
770 def CTERMNE_XX : sve_int_cterm<0b1, 0b1, "ctermne", GPR64>;
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td410 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
750 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
751 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
753 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
754 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
756 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
757 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
759 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
789 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
790 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64;
[all …]
H A DMipsCondMov.td203 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
205 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
207 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
209 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
211 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
213 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
215 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
217 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
219 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
228 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
[all …]
H A DMipsRegisterInfo.td348 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
644 def GPR64Opnd : RegisterOperand<GPR64> {
H A DMipsInstrInfo.td2336 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
2337 GPR64:$dst),
2338 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
H A DMipsMSAInstrInfo.td3932 GPR64), [HasMSA, IsGP64bit]>;
3953 GPR64), [HasMSA, IsGP64bit]>;
4001 GPR64), [HasMSA, IsGP64bit]>;
4038 GPR64),
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td61 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
69 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
80 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
85 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
86 !cast<GPR64>("R"#I#"D")>;
H A DSystemZFrameLowering.cpp119 unsigned GPR64, bool IsImplicit) { in addSavedGPR() argument
122 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR()
123 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR()
125 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
127 MBB.addLiveIn(GPR64); in addSavedGPR()
/freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/
H A DRegisterContextFreeBSD_powerpc.cpp56 } GPR64; typedef
226 return sizeof(GPR64); in GetGPRSize()
H A DRegisterInfos_powerpc.h189 #define GPR GPR64
201 #define GPR GPR64
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86CallingConv.td94 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)