Searched refs:FinalReg (Results 1 – 2 of 2) sorted by relevance
1285 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local1306 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()1307 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()1309 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()1319 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
596 FinalReg = InProlog ? (unsigned)X86::RDX in emitStackProbeInline() local657 BuildMI(&MBB, DL, TII.get(X86::CMOVB64rr), FinalReg) in emitStackProbeInline()674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInline()679 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInline()681 .addReg(FinalReg) in emitStackProbeInline()