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Searched refs:FPR64 (Results 1 – 9 of 9) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td36 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
41 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
56 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
234 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
238 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
239 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
242 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
243 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
246 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
247 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
[all …]
H A DRISCVInstrInfoC.td441 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000> {
494 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000> {
658 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
659 (C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
697 def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
698 (C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
H A DRISCVRegisterInfo.td219 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3170 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
3171 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3178 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
3179 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3184 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
3185 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
3849 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3859 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3863 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3867 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
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H A DAArch64InstrFormats.td4654 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
4699 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
6345 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6351 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6356 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6383 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
6400 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
6573 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
6618 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
7659 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
[all …]
H A DAArch64RegisterInfo.td421 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
439 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
441 [(rotl FPR64, 0), (rotl FPR64, 1),
442 (rotl FPR64, 2)]>;
444 [(rotl FPR64, 0), (rotl FPR64, 1),
445 (rotl FPR64, 2), (rotl FPR64, 3)]>;
486 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
616 defm VecListOne : VectorList<1, FPR64, FPR128>;
640 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
641 let ParserMatchClass = FPRAsmOperand<"FPR64">;
H A DAArch64FrameLowering.cpp1604 enum RegType { GPR, FPR64, FPR128 } Type; enumerator
1646 RPI.Type = RegPairInfo::FPR64; in computeCalleeSaveRegisterPairs()
1661 case RegPairInfo::FPR64: in computeCalleeSaveRegisterPairs()
1801 case RegPairInfo::FPR64: in spillCalleeSavedRegisters()
1892 case RegPairInfo::FPR64: in restoreCalleeSavedRegisters()
H A DSVEInstrFormats.td852 def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
2296 def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>;
2329 def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>;
3195 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
3277 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
3414 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
4302 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
4303 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
4304 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
4308 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
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/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td185 class FPR64<bits<16> num, string n, FPR32 high>
192 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
202 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
207 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
212 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
213 !cast<FPR64>("F"#I#"D")>;
227 // A full 128-bit vector register, with an FPR64 as its high part.
228 class VR128<bits<16> num, string n, FPR64 high>
236 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,