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Searched refs:FP (Results 1 – 25 of 273) sorted by relevance

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/freebsd-12.1/contrib/binutils/opcodes/
H A Dalpha-opc.c347 #define FP(oo,fff) FP_(oo,fff), FP_MASK macro
729 { "addf", FP(0x15,0x080), BASE, ARG_FP },
731 { "subf", FP(0x15,0x081), BASE, ARG_FP },
732 { "mulf", FP(0x15,0x082), BASE, ARG_FP },
733 { "divf", FP(0x15,0x083), BASE, ARG_FP },
735 { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
737 { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
738 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
739 { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
850 { "adds", FP(0x16,0x080), BASE, ARG_FP },
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp465 if (BB == FP.SplitB || BB == FP.TrueB || BB == FP.FalseB) in computePhiCost()
508 if (MBPI && FP.TrueB && !FP.FalseB && in isProfitable()
513 if (MBPI && !FP.TrueB && FP.FalseB && in isProfitable()
518 if (FP.TrueB && FP.FalseB) { in isProfitable()
570 TotalPh = computePhiCost(FP.JoinB, FP); in isProfitable()
867 predicateBlockNB(FP.SplitB, OldTI, FP.TrueB, FP.PredR, true); in convert()
872 predicateBlockNB(FP.SplitB, At, FP.FalseB, FP.PredR, false); in convert()
879 FP.SplitB->erase(OldTI, FP.SplitB->end()); in convert()
896 if (T != FP.TrueB && T != FP.FalseB) { in convert()
911 FP.SplitB->addSuccessor(FP.JoinB); in convert()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleV6.td228 // Single-precision FP ALU
231 // Double-precision FP ALU
240 // Single-precision FP MAC
243 // Double-precision FP MAC
252 // Single-precision FP DIV
255 // Double-precision FP DIV
258 // Single-precision FP SQRT
261 // Double-precision FP SQRT
276 // Single-precision FP Load
282 // FP Load Multiple
[all …]
H A DARMScheduleA8.td303 // Single-precision FP ALU
307 // Double-precision FP ALU
321 // Single-precision FP MAC
325 // Double-precision FP MAC
339 // Single-precision FP DIV
344 // Double-precision FP DIV
349 // Single-precision FP SQRT
393 // FP Load Multiple
422 // FP Store Multiple
779 // Quad-register FP Unary
[all …]
H A DARMScheduleA9.td568 // Single-precision FP ALU
576 // Double-precision FP ALU
600 // Single-precision FP MAC
608 // Double-precision FP MAC
632 // Single-precision FP DIV
640 // Double-precision FP DIV
648 // Single-precision FP SQRT
718 // FP Load Multiple
756 // FP Store Multiple
1646 // Quad-register FP Unary
[all …]
/freebsd-12.1/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-c64x.pl105 STDW A3:A2,*FP[-7]
410 || STDW A13:A12,*FP[-4]
412 || STDW A11:A10,*FP[-5]
414 || STW A14,*FP[-6]
524 || LDW *FP[-6],A14
563 || STW A14,*FP[-6]
722 || LDW *FP[-6],A14
765 || STW A14,*FP[-2]
766 STDW A13:A12,*FP[-2]
838 LDDW *FP[-2],A13:A12
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetOptionsImpl.cpp46 StringRef FP = F.getFnAttribute("frame-pointer").getValueAsString(); in DisableFramePointerElim() local
47 if (FP == "all") in DisableFramePointerElim()
49 if (FP == "non-leaf") in DisableFramePointerElim()
51 if (FP == "none") in DisableFramePointerElim()
H A DRegisterUsageInfo.cpp61 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
62 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
66 PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) { in getRegUsageInfo() argument
67 auto It = RegMasks.find(&FP); in getRegUsageInfo()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/InstPrinter/
H A DWebAssemblyInstPrinter.cpp194 static std::string toString(const APFloat &FP) { in toString() argument
196 if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && in toString()
197 !FP.bitwiseIsEqual( in toString()
198 APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) { in toString()
199 APInt AI = FP.bitcastToAPInt(); in toString()
210 auto Written = FP.convertToHexString( in toString()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td39 // Port 0: ALU, FP/SIMD.
1091 // FP absolute value
1092 // FP min/max
1093 // FP negate
1099 // FP arithmetic
1102 // FP compare
1108 // FP Mul, Div, Sqrt
1160 // FP multiply
1188 // FP select
1203 // FP move, immed
[all …]
H A DAArch64SchedExynosM3.td43 def M3PipeF0 : ProcResource<1>; // FP #0
225 // FP data instructions.
232 // FP miscellaneous instructions.
237 // FP load instructions.
240 // FP store instructions.
245 // ASIMD FP instructions.
522 // FP data instructions.
537 // FP miscellaneous instructions.
551 // FP load instructions.
574 // FP store instructions.
[all …]
H A DAArch64SchedA57.td428 // ASIMD FP arith, normal, D-form
438 // ASIMD FP compare, D-form
440 // ASIMD FP compare, Q-form
450 // ASIMD FP divide, D-form, F32
452 // ASIMD FP divide, Q-form, F32
454 // ASIMD FP divide, Q-form, F64
473 // ASIMD FP max/min, reduce
476 // ASIMD FP multiply, D-form, FZ
478 // ASIMD FP multiply, Q-form, FZ
489 // ASIMD FP round, D-form
[all …]
H A DAArch64SchedExynosM4.td50 def M4PipeF0 : ProcResource<1>; // FP #0
532 // FP data instructions.
538 // FP miscellaneous instructions.
543 // FP load instructions.
546 // FP store instructions.
549 // ASIMD FP instructions.
619 // FP data instructions.
649 // FP miscellaneous instructions.
666 // FP load instructions.
695 // FP store instructions.
[all …]
/freebsd-12.1/sys/arm/arm/
H A Ddb_trace.c88 state->registers[SP], state->registers[FP]); in db_stack_trace_cmd()
92 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
162 state.registers[FP] = ctx->pcb_regs.sf_r11; in db_trace_thread()
182 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in db_trace_self()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp115 .addReg(Lanai::FP) in emitPrologue()
123 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP) in emitPrologue()
188 .addReg(Lanai::FP) in emitEpilogue()
192 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP) in emitEpilogue()
193 .addReg(Lanai::FP) in emitEpilogue()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp43 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
53 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
91 Reserved.set(MSP430::FP); in getReservedRegs()
116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); in eliminateFrameIndex()
160 return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP; in getFrameRegister()
H A DMSP430FrameLowering.cpp68 .addReg(MSP430::FP, RegState::Kill); in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
77 I->addLiveIn(MSP430::FP); in emitPrologue()
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
158 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); in emitEpilogue()
/freebsd-12.1/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-c64xplus.pl117 || [A2] STDW A13:A12,*FP[-3]
118 [A2] STDW A11:A10,*FP[-4]
252 LDDW *FP[-4],A11:A10 ; ABI says so
253 LDDW *FP[-3],A13:A12
/freebsd-12.1/contrib/llvm/lib/IR/
H A DLegacyPassManager.cpp435 return FP; in getContainedManager()
1605 FP->dumpPassStructure(Offset + 1); in dumpPassStructure()
1606 dumpLastUses(FP, Offset+1); in dumpPassStructure()
1637 dumpRequiredSet(FP); in runOnFunction()
1639 initializeAnalysisImpl(FP); in runOnFunction()
1642 PassManagerPrettyStackEntry X(FP, F); in runOnFunction()
1664 dumpPreservedSet(FP); in runOnFunction()
1665 dumpUsedSet(FP); in runOnFunction()
1667 verifyPreservedAnalysis(FP); in runOnFunction()
1668 removeNotPreservedAnalysis(FP); in runOnFunction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp200 Reserved.set(Mips::FP); in getReservedRegs()
306 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : in getFrameRegister()
322 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; in canRealignStack() local
331 if (!MF.getRegInfo().canReserveReg(FP)) in canRealignStack()
/freebsd-12.1/contrib/gcc/config/sparc/
H A Dsparc.opt24 Use hardware FP
28 Use hardware FP
32 Do not use hardware FP
48 Use hardware quad FP instructions
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DRegisterUsageInfo.h51 void storeUpdateRegUsageInfo(const Function &FP,
56 ArrayRef<uint32_t> getRegUsageInfo(const Function &FP);
H A DCommandFlags.inc117 static cl::opt<llvm::FramePointer::FP> FramePointerUsage(
130 cl::desc("Enable optimizations that may decrease FP precision"),
135 cl::desc("Enable FP math optimizations that assume no +-Infs"),
140 cl::desc("Enable FP math optimizations that assume no NaNs"),
145 cl::desc("Enable FP math optimizations that assume "
151 cl::desc("Enable setting the FP exceptions build "
179 "Hard float ABI (uses FP registers)")));
182 "fp-contract", cl::desc("Enable aggressive formation of fused FP ops"),
185 clEnumValN(FPOpFusion::Fast, "fast", "Fuse FP ops whenever profitable"),
186 clEnumValN(FPOpFusion::Standard, "on", "Only fuse 'blessed' FP ops."),
[all …]
/freebsd-12.1/contrib/libc++/src/
H A Dchrono.cpp158 typedef steady_clock::rep (*FP)(); typedef
161 FP
174 static FP fp = init_steady_clock(); in now()
/freebsd-12.1/share/syscons/fonts/
H A Diso02-8x14.fnt30 M``````#&QL;6UM;^[FP``````,;&;#@X.&S&Q@``````9F9F9CP8&!@\````
69 M`'S&QL;&QL9\````-FP`?,;&QL;&QGP`````Q@!\QL;&QL;&?```````````
71 MQL9\````-FP`QL;&QL;&QGP`````Q@#&QL;&QL;&?`````P8`&9F9F8\&!@\
79 M`'S&QL;&?```````-FP`?,;&QL9\``````#&``!\QL;&QGP`````````&!@`

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