Searched refs:FIOp (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 182 int SPAdj, unsigned FIOp, in eliminateFrameIndex() argument
196 int FI = MI.getOperand(FIOp).getIndex(); in eliminateFrameIndex()
201 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm(); in eliminateFrameIndex()
208 MI.getOperand(FIOp).ChangeToImmediate(RealOffset); in eliminateFrameIndex()
209 MI.RemoveOperand(FIOp+1); in eliminateFrameIndex()
231 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill); in eliminateFrameIndex()
232 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); in eliminateFrameIndex()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 359 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in resolveFrameIndex() local
360 assert(FIOp && FIOp->isFI() && "frame index must be address operand"); in resolveFrameIndex()
371 FIOp->ChangeToRegister(BaseReg, false); in resolveFrameIndex()
1001 MachineOperand &FIOp = MI->getOperand(FIOperandNum); in eliminateFrameIndex() local
1126 FIOp.ChangeToRegister(ResultReg, false, false, true); in eliminateFrameIndex()
1155 FIOp.ChangeToImmediate(Offset); in eliminateFrameIndex()
1156 if (!TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) { in eliminateFrameIndex()
1160 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2968 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
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