1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1996 Gardner Buchanan <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Gardner Buchanan. 18 * 4. The name of Gardner Buchanan may not be used to endorse or promote 19 * products derived from this software without specific prior written 20 * permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * This file contains register information and access macros for 38 * the SMC91xxx chipset. 39 * 40 * Information contained in this file was obtained from the SMC91C92 41 * and SMC91C94 manuals from SMC. You will need one of these in order 42 * to make any meaningful changes to this driver. Information about 43 * obtaining one can be found at http://www.smc.com in the components 44 * division. 45 * 46 * This FreeBSD driver is derived in part from the smc9194 Linux driver 47 * by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 48 * It is also derived in part from the FreeBSD ep (3C509) driver which 49 * is Copyright (c) 1993 Herb Peyerl ([email protected]) All rights 50 * reserved. 51 * 52 */ 53 #ifndef _IF_SNREG_H_ 54 #define _IF_SNREG_H_ 55 56 /* 57 * Wait time for memory to be free. This probably shouldn't be 58 * tuned that much, as waiting for this means nothing else happens 59 * in the system 60 */ 61 #define MEMORY_WAIT_TIME 1000 62 63 64 /* The SMC91xxx uses 16 I/O ports 65 */ 66 #define SMC_IO_EXTENT 16 67 68 69 /* 70 * A description of the SMC registers is probably in order here, 71 * although for details, the SMC datasheet is invaluable. 72 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet 73 * Controller With RAM", Rev. 12/0/94. Constant definitions I give 74 * here are loosely based on the mnemonic names given to them in the 75 * data sheet, but there are many exceptions. 76 * 77 * Basically, the chip has 4 banks of registers (0 to 3), which 78 * are accessed by writing a number into the BANK_SELECT register 79 * (I also use a SMC_SELECT_BANK macro for this). Registers are 80 * either Byte or Word sized. My constant definitions end in _B 81 * or _W as appropriate. 82 * 83 * The banks are arranged so that for most purposes, bank 2 is all 84 * that is needed for normal run time tasks. 85 */ 86 87 /* 88 * Bank Select Register. This also doubles as 89 * a chip identification register. This register 90 * is mapped at the same position in all banks. 91 */ 92 #define BANK_SELECT_REG_W 0x0e 93 #define BSR_DETECT_MASK 0xff00 94 #define BSR_DETECT_VALUE 0x3300 95 96 97 /* BANK 0 98 */ 99 100 /* Transmit Control Register controls some aspects of the transmit 101 * behavior of the Ethernet Protocol Handler. 102 */ 103 #define TXMIT_CONTROL_REG_W 0x00 104 105 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ 106 #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */ 107 #define TCR_FORCOL 0x0004 /* Force Collision on next TX */ 108 #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */ 109 #define TCR_NOCRC 0x0100 /* Do not append CRC */ 110 #define TCR_MON_CSN 0x0400 /* monitors the carrier status */ 111 #define TCR_FDUPLX 0x0800 /* receive packets sent out */ 112 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ 113 #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */ 114 115 116 /* Status of the last transmitted frame and instantaneous status of 117 * the Ethernet Protocol Handler jumbled together. In auto-release 118 * mode this information is simply discarded after each TX. This info 119 * is copied to the status word of in-memory packets after transmit 120 * where relevant statuses can be checked. 121 */ 122 #define EPH_STATUS_REG_W 0x02 123 124 #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */ 125 #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */ 126 #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */ 127 #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */ 128 #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */ 129 #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */ 130 #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */ 131 #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */ 132 #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */ 133 #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */ 134 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER 135 * times */ 136 #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */ 137 #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */ 138 #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */ 139 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 140 141 142 /* Receiver Control Register controls some aspects of the receive 143 * behavior of the Ethernet Protocol Handler. 144 */ 145 #define RECV_CONTROL_REG_W 0x04 146 147 #define RCR_RX_ABORT 0x0001 /* Received huge packet */ 148 #define RCR_PROMISC 0x0002 /* enable promiscuous mode */ 149 #define RCR_ALMUL 0x0004 /* receive all multicast packets */ 150 #define RCR_ENABLE 0x0100 /* IFF this is set, we can receive packets */ 151 #define RCR_STRIP_CRC 0x0200 /* strips CRC */ 152 #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */ 153 #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */ 154 #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */ 155 156 157 /* TX Statistics counters 158 */ 159 #define COUNTER_REG_W 0x06 160 161 #define ECR_COLN_MASK 0x000f /* Vanilla collisions */ 162 #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */ 163 #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */ 164 #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */ 165 166 /* Memory Information 167 */ 168 #define MEM_INFO_REG_W 0x08 169 170 #define MIR_FREE_MASK 0xff00 /* Free memory pages available */ 171 #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */ 172 173 /* Memory Configuration 174 */ 175 #define MEM_CFG_REG_W 0x0a 176 177 #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */ 178 179 180 /* Bank 0, Register 0x0c is unised in the SMC91C92 181 */ 182 183 184 /* BANK 1 185 */ 186 187 /* Adapter configuration 188 */ 189 #define CONFIG_REG_W 0x00 190 191 #define CR_INT_SEL0 0x0002 /* Interrupt selector */ 192 #define CR_INT_SEL1 0x0004 /* Interrupt selector */ 193 #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */ 194 #define CR_16BIT 0x0080 /* Bus width */ 195 #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */ 196 #define CR_SET_SQLCH 0x0200 /* Squelch level */ 197 #define CR_FULL_STEP 0x0400 /* AUI signalling mode */ 198 #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */ 199 200 /* The contents of this port are used by the adapter 201 * to decode its I/O address. We use it as a varification 202 * that the adapter is detected properly when probing. 203 */ 204 #define BASE_ADDR_REG_W 0x02 /* The select IO Base addr. */ 205 206 /* These registers hold the Ethernet MAC address. 207 */ 208 #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */ 209 #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */ 210 #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */ 211 212 /* General purpose register used for talking to the EEPROM. 213 */ 214 #define GENERAL_REG_W 0x0a 215 216 /* Control register used for talking to the EEPROM and 217 * setting some EPH functions. 218 */ 219 #define CONTROL_REG_W 0x0c 220 #define CTR_STORE 0x0001 /* Store something to EEPROM */ 221 #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */ 222 #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */ 223 #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */ 224 #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */ 225 #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */ 226 #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */ 227 #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */ 228 #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */ 229 230 231 /* BANK 2 232 */ 233 234 /* Memory Management Unit Control Register 235 * Controls allocation of memory to receive and 236 * transmit functions. 237 */ 238 #define MMU_CMD_REG_W 0x00 239 #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */ 240 241 /* MMU Commands: 242 */ 243 #define MMUCR_NOP 0x0000 /* Do nothing */ 244 #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */ 245 #define MMUCR_RESET 0x0040 /* Reset MMU State */ 246 #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */ 247 #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */ 248 #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */ 249 #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */ 250 #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */ 251 252 /* Packet Number at TX Area 253 */ 254 #define PACKET_NUM_REG_B 0x02 255 256 /* Packet number resulting from MMUCR_ALLOC 257 */ 258 #define ALLOC_RESULT_REG_B 0x03 259 #define ARR_FAILED 0x80 260 261 /* Transmit and receive queue heads 262 */ 263 #define FIFO_PORTS_REG_W 0x04 264 #define FIFO_REMPTY 0x8000 265 #define FIFO_TEMPTY 0x0080 266 #define FIFO_RX_MASK 0x7f00 267 #define FIFO_TX_MASK 0x007f 268 269 /* The address within the packet for reading/writing. The 270 * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number 271 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK. 272 * When PTR_RCV==0, the packet number to be written is found 273 * in the PACKET_NUM_REG_B. 274 */ 275 #define POINTER_REG_W 0x06 276 #define PTR_READ 0x2000 /* Intended access mode */ 277 #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */ 278 #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */ 279 280 /* Data I/O register to be used in conjunction with 281 * The pointer register to read and write data from the 282 * card. The same register can be used for byte and word 283 * ops. 284 */ 285 #define DATA_REG_W 0x08 286 #define DATA_REG_B 0x08 287 #define DATA_1_REG_B 0x08 288 #define DATA_2_REG_B 0x0a 289 290 /* Sense interrupt status (READ) 291 */ 292 #define INTR_STAT_REG_B 0x0c 293 294 /* Acknowledge interrupt sources (WRITE) 295 */ 296 #define INTR_ACK_REG_B 0x0c 297 298 /* Interrupt mask. Bit set indicates interrupt allowed. 299 */ 300 #define INTR_MASK_REG_B 0x0d 301 302 /* Interrupts 303 */ 304 #define IM_RCV_INT 0x01 /* A packet has been received */ 305 #define IM_TX_INT 0x02 /* Packet TX complete */ 306 #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */ 307 #define IM_ALLOC_INT 0x08 /* Memory allocation completed */ 308 #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */ 309 #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */ 310 #define IM_ERCV_INT 0x40 /* not on SMC9192 */ 311 312 /* BANK 3 313 */ 314 315 /* Multicast subscriptions. 316 * The multicast handling in the SMC90Cxx is quite complicated. A table 317 * of multicast address subscriptions is provided and a clever way of 318 * speeding the search of that table by hashing is implemented in the 319 * hardware. I have ignored this and simply subscribed to all multicasts 320 * and let the kernel deal with the results. 321 */ 322 #define MULTICAST1_REG_W 0x00 323 #define MULTICAST2_REG_W 0x02 324 #define MULTICAST3_REG_W 0x04 325 #define MULTICAST4_REG_W 0x06 326 327 /* These registers do not exist on SMC9192, or at least 328 * are not documented in the SMC91C92 data sheet. 329 * The REVISION_REG_W register does however seem to work. 330 */ 331 #define MGMT_REG_W 0x08 332 #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */ 333 #define ERCV_REG_W 0x0c 334 335 /* These are constants expected to be found in the 336 * chip id register. 337 */ 338 #define CHIP_9190 3 339 #define CHIP_9194 4 340 #define CHIP_9195 5 341 #define CHIP_91100 7 342 #define CHIP_91100FD 8 343 344 /* When packets are stuffed into the card or sucked out of the card 345 * they are set up more or less as follows: 346 * 347 * Addr msbyte lsbyte 348 * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status 349 * 02 RRRRR - RESERVED (unused) 350 * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored) 351 * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS 352 * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address) 353 * 08 DDDDDDDD DDDDDDDD 354 * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS 355 * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address) 356 * 0E SSSSSSSS SSSSSSSS 357 * 10 PPPPPPPP PPPPPPPP 358 * .. PPPPPPPP PPPPPPPP 359 * C-2 CCCCCCCC - CONTROL BYTE 360 * C-2 PPPPPPPP - Last data byte (If odd length) 361 * 362 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register 363 * during transmit and is composed of another set of bits described 364 * below during receive. 365 */ 366 367 368 /* Receive status bits. These values are found in the status word 369 * field of a received packet. For receive packets I use the RS_ODDFRAME 370 * to detect whether a frame has an extra byte on it. The CTLB_ODD 371 * bit of the control byte tells the same thing. 372 */ 373 #define RS_MULTICAST 0x0001 /* Packet is multicast */ 374 #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ 375 #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ 376 #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ 377 #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ 378 #define RS_BADCRC 0x2000 /* Frame had CRC error */ 379 #define RS_ALGNERR 0x8000 /* Frame had alignment error */ 380 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 381 382 #define RLEN_MASK 0x07ff /* Significant length bits in RX length */ 383 384 /* The control byte has the following significant bits. 385 * For transmit, the CTLB_ODD bit specifies whether an extra byte 386 * is present in the frame. Bit 0 of the byte count field is 387 * ignored. I just pad every frame to even length and forget about 388 * it. 389 */ 390 #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */ 391 #define CTLB_ODD 0x20 /* The packet length is ODD */ 392 393 394 /* 395 * I define some macros to make it easier to do somewhat common 396 * or slightly complicated, repeated tasks. 397 */ 398 399 /* Select a register bank, 0 to 3 400 */ 401 #define SMC_SELECT_BANK(sc, x) { CSR_WRITE_2(sc, BANK_SELECT_REG_W, (x)); } 402 403 /* Define a small delay for the reset 404 */ 405 #define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \ 406 CSR_READ_2(sc, RECV_CONTROL_REG_W); \ 407 CSR_READ_2(sc, RECV_CONTROL_REG_W); } 408 409 #endif /* _IF_SNREG_H_ */ 410