Searched refs:FGETSIGN (Results 1 – 9 of 9) sorted by relevance
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 316 FGETSIGN, enumerator
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 256 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
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| H A D | TargetLowering.cpp | 1282 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits() 1283 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits() 1290 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); in SimplifyDemandedBits()
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| H A D | SelectionDAG.cpp | 2864 case ISD::FGETSIGN: in computeKnownBits()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 599 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 431 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 885 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering() 937 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 554 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering() 555 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering() 26231 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
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