Searched refs:ExtVec (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 437 SDValue ExtVec; in buildHvxVectorReg() local
438 if (IsBuildFromExtracts(ExtVec, ExtIdx)) { in buildHvxVectorReg()
439 MVT ExtTy = ty(ExtVec); in buildHvxVectorReg()
465 SDValue S = DAG.getVectorShuffle(ExtTy, dl, ExtVec, in buildHvxVectorReg()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 16693 SDValue ExtVec = Op.getOperand(0); in combineConcatVectorOfExtracts() local
16697 EVT ExtVT = ExtVec.getValueType(); in combineConcatVectorOfExtracts()
16698 ExtVec = peekThroughBitcasts(ExtVec); in combineConcatVectorOfExtracts()
16701 if (ExtVec.isUndef()) { in combineConcatVectorOfExtracts()
16725 if (SV0.isUndef() || SV0 == ExtVec) { in combineConcatVectorOfExtracts()
16726 SV0 = ExtVec; in combineConcatVectorOfExtracts()
16729 } else if (SV1.isUndef() || SV1 == ExtVec) { in combineConcatVectorOfExtracts()
16730 SV1 = ExtVec; in combineConcatVectorOfExtracts()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7801 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm); in LowerBUILD_VECTORvXi1() local
7802 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
7848 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm); in LowerBUILD_VECTORvXi1() local
7849 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
20007 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect); in LowerSELECT() local
20008 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec, in LowerSELECT()
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