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Searched refs:ExtTy (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMCodeGenPrepare.cpp117 IntegerType *ExtTy = nullptr; member in __anon96a67c9e0111::IRPromoter
134 ExtTy(Type::getInt32Ty(Ctx)) { } in IRPromoter()
529 assert(V->getType() != ExtTy && "zext already extends to i32"); in ExtendSources()
535 Value *ZExt = Builder.CreateZExt(V, ExtTy); in ExtendSources()
580 if ((Op->getType() == ExtTy) || !isa<IntegerType>(Op->getType())) in PromoteTree()
584 Constant *NewConst = ConstantExpr::getZExt(Const, ExtTy); in PromoteTree()
587 I->setOperand(i, UndefValue::get(ExtTy)); in PromoteTree()
591 I->mutateType(ExtTy); in PromoteTree()
693 if (ZExt->getDestTy() != ExtTy) in Cleanup()
708 assert(Trunc->getOperand(0)->getType() == ExtTy && in Cleanup()
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H A DARMISelLowering.cpp7249 const EVT &ExtTy, in AddRequiredExtensionForVMULL() argument
7254 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp439 MVT ExtTy = ty(ExtVec); in buildHvxVectorReg() local
440 unsigned ExtLen = ExtTy.getVectorNumElements(); in buildHvxVectorReg()
465 SDValue S = DAG.getVectorShuffle(ExtTy, dl, ExtVec, in buildHvxVectorReg()
466 DAG.getUNDEF(ExtTy), Mask); in buildHvxVectorReg()
1282 MVT ExtTy = typeExtElem(ResTy, 2); in LowerHvxMul() local
1285 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMul()
1339 MVT ExtTy = typeExtElem(ResTy, 2); in LowerHvxMulh() local
1343 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
H A DHexagonISelLowering.h307 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DHexagonISelLowering.cpp3092 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth() argument
3094 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3431 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in addPromotedInst() local
3436 if (It->second.getInt() == ExtTy) in addPromotedInst()
3442 ExtTy = BothExtension; in addPromotedInst()
3454 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in getOrigType() local
3456 if (It != PromotedInsts.end() && It->second.getInt() == ExtTy) in getOrigType()
3668 Type *ExtTy = Ext->getType(); in getAction() local
4894 Type *ExtTy = FirstUser->getType(); in hasSameExtUse() local
4901 if (CurTy == ExtTy) in hasSameExtUse()
4920 if (ExtTy->getScalarType()->getIntegerBitWidth() > in hasSameExtUse()
4923 LargeTy = ExtTy; in hasSameExtUse()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h541 uint16_t ExtTy : 2; // enum ISD::LoadExtType
2084 LoadSDNodeBits.ExtTy = ETy;
2093 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2170 LoadSDNodeBits.ExtTy = ETy;
2175 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
H A DTargetLowering.h1258 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h319 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DAArch64ISelLowering.cpp2525 const EVT &ExtTy, in addRequiredExtensionForVectorMULL() argument
2530 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
8127 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
8130 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
8135 if (ExtTy != ISD::NON_EXTLOAD) in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DScalarEvolution.cpp3169 IntegerType *ExtTy = in getUDivExpr() local
3178 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3179 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3180 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3192 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3193 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3194 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3207 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
3208 if (getZeroExtendExpr(M, ExtTy) == getMulExpr(Operands)) in getUDivExpr()
3240 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h1030 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DX86InstrSSE.td5250 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
5267 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5271 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5273 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5276 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5278 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5281 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5321 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5342 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5346 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
[all …]
H A DX86InstrAVX512.td9866 SDNode OpNode, SDNode InVecNode, string ExtTy,
9867 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9885 SDNode OpNode, SDNode InVecNode, string ExtTy,
9886 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9904 SDNode OpNode, SDNode InVecNode, string ExtTy,
9905 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9923 SDNode OpNode, SDNode InVecNode, string ExtTy,
9924 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
9942 SDNode OpNode, SDNode InVecNode, string ExtTy,
9943 X86FoldableSchedWrite sched, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
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H A DX86ISelLowering.cpp4832 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
36590 static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, in lowerX86CmpEqZeroToCtlzSrl() argument
36602 return DAG.getZExtOrTrunc(Scc, dl, ExtTy); in lowerX86CmpEqZeroToCtlzSrl()
/freebsd-12.1/contrib/llvm/lib/IR/
H A DAutoUpgrade.cpp1632 Type *ExtTy = Type::getInt32Ty(C); in UpgradeIntrinsicCall() local
1634 ExtTy = Type::getInt64Ty(C); in UpgradeIntrinsicCall()
1636 ExtTy->getPrimitiveSizeInBits(); in UpgradeIntrinsicCall()
1637 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); in UpgradeIntrinsicCall()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1827 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateReg() argument
1835 Op->Reg.ShiftExtend.Type = ExtTy; in CreateReg()
1846 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateVectorReg() argument
1852 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp656 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
659 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp6873 ISD::LoadExtType ExtTy, bool isExpanding) { in getMaskedLoad() argument
6880 dl.getIROrder(), VTs, ExtTy, isExpanding, MemVT, MMO)); in getMaskedLoad()
6888 ExtTy, isExpanding, MemVT, MMO); in getMaskedLoad()
H A DDAGCombiner.cpp15597 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad() local
15599 if (!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT)) in scalarizeExtractedVectorLoad()