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Searched refs:ExtOpc (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp868 switch (ExtOpc) { in getRegOffOpcode()
881 switch (ExtOpc) { in getRegOffOpcode()
955 return ExtOpc; in getRegOffOpcode()
965 switch (ExtOpc) { in getDirectRegReplacement()
1588 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExact() local
1615 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) { in replaceInstrExact()
1706 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExpr() local
1708 if (ExtOpc == Hexagon::A2_tfrsi) { in replaceInstrExpr()
1753 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) { in replaceInstrExpr()
1771 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii || in replaceInstrExpr()
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H A DHexagonBitSimplify.cpp2510 unsigned ExtOpc = 0; in simplifyExtractLow() local
2513 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2515 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2517 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2519 if (ExtOpc == 0) { in simplifyExtractLow()
2520 ExtOpc = in simplifyExtractLow()
2532 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2536 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2548 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2550 switch (ExtOpc) { in simplifyExtractLow()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp347 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
350 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
351 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
361 Opcode = ExtOpc; in buildExtOrTrunc()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h514 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1112 unsigned ExtOpc = in PromoteOperand() local
1114 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
8208 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
8222 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
8224 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
8535 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
8546 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
8556 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp18024 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
18031 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
18032 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
20338 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
20341 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
24664 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift() local
24665 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
38387 unsigned ExtOpc = LHS.getOpcode(); in combinePMULH() local
38388 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combinePMULH()
38389 RHS.getOpcode() != ExtOpc) in combinePMULH()
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