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Searched refs:Enc (Results 1 – 18 of 18) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td18 class Wi<bits<16> Enc, string n> : Register<n> {
19 let HWEncoding = Enc;
25 class Ri<bits<16> Enc, string n, list<Register> subregs>
27 let HWEncoding = Enc;
/freebsd-12.1/contrib/llvm/tools/lld/ELF/
H A DEhFrame.cpp123 static size_t getAugPSize(unsigned Enc) { in getAugPSize() argument
124 switch (Enc & 0x0f) { in getAugPSize()
142 uint8_t Enc = readByte(); in skipAugP() local
143 if ((Enc & 0xf0) == DW_EH_PE_aligned) in skipAugP()
145 size_t Size = getAugPSize(Enc); in skipAugP()
H A DSyntheticSections.cpp508 uint8_t Enc = getFdeEncoding(Rec->Cie); in getFdeData() local
510 uint64_t Pc = getFdePc(Buf, Fde->OutputOff, Enc); in getFdeData()
556 uint8_t Enc) const { in getFdePc()
560 uint64_t Addr = readFdeAddr(Buf + Off, Enc & 0xf); in getFdePc()
561 if ((Enc & 0x70) == DW_EH_PE_absptr) in getFdePc()
563 if ((Enc & 0x70) == DW_EH_PE_pcrel) in getFdePc()
H A DSyntheticSections.h103 uint64_t getFdePc(uint8_t *Buf, size_t Off, uint8_t Enc) const;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp348 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getSDWASrcEncoding() local
349 if (Enc != ~0U && Enc != 255) { in getSDWASrcEncoding()
350 return Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
431 uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); in getMachineOpValue() local
432 if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4)) in getMachineOpValue()
433 return Enc; in getMachineOpValue()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td30 class MipsReg<bits<16> Enc, string n> : Register<n> {
31 let HWEncoding = Enc;
37 let HWEncoding = Enc;
42 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
46 : MipsRegWithSubRegs<Enc, n, subregs> {
51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
55 : MipsRegWithSubRegs<Enc, n, subregs> {
61 : MipsRegWithSubRegs<Enc, n, subregs> {
68 : MipsRegWithSubRegs<Enc, n, subregs> {
74 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td14 class SparcReg<bits<16> Enc, string n> : Register<n> {
15 let HWEncoding = Enc;
19 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
20 let HWEncoding = Enc;
33 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
36 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
42 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
/freebsd-12.1/contrib/llvm/include/llvm/Bitcode/
H A DBitCodes.h97 unsigned Enc : 3; // The encoding to use. variable
109 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
118 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DTargetInfo.cpp8503 return Enc < rhs.Enc; in operator <()
8773 Enc += '('; in appendRecordType()
8776 Enc += "){"; in appendRecordType()
8806 Enc += '}'; in appendRecordType()
8823 Enc += "e("; in appendEnumType()
8826 Enc += "){"; in appendEnumType()
8849 Enc += '}'; in appendEnumType()
8935 Enc += ')'; in appendPointerType()
8951 Enc += ':'; in appendArrayType()
8956 Enc += ')'; in appendArrayType()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp160 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
161 if (Enc != -1) in LowerARMMachineInstrToMCInst()
162 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
H A DARMRegisterInfo.td17 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td15 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
16 let HWEncoding{4-0} = Enc;
20 class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
21 let HWEncoding{4-0} = Enc;
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp479 uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
486 } else if (Enc != X86Local::XOP && Enc != X86Local::VEX && in addEntryWithFlags()
487 Enc != X86Local::EVEX) { in addEntryWithFlags()
/freebsd-12.1/crypto/openssl/doc/man3/
H A DSSL_CIPHER_get_name.pod141 =item Enc=<symmetric encryption method>
153 ECDHE-RSA-AES256-GCM-SHA256 TLSv1.2 Kx=ECDH Au=RSA Enc=AESGCM(256) Mac=AEAD
154 RSA-PSK-AES256-CBC-SHA384 TLSv1.0 Kx=RSAPSK Au=RSA Enc=AES(256) Mac=SHA384
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInsertWaitcnts.cpp1056 unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); in generateWaitcntInstBefore() local
1058 OldWaitcntInstr->getOperand(0).setImm(Enc); in generateWaitcntInstBefore()
1066 .addImm(Enc); in generateWaitcntInstBefore()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86RegisterInfo.td16 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
18 let HWEncoding = Enc;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2119 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands() local
2120 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
2126 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands() local
2127 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
4725 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm() local
4726 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { in parseModImm()
4728 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
4729 (Enc & 0xF00) >> 7, in parseModImm()
7219 unsigned Enc = Inst.getOperand(2).getImm(); in processInstruction() local
7221 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); in processInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp855 uint64_t OldImm = Imm, NewImm, Enc; in optimizeLogicalImm() local
937 Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size); in optimizeLogicalImm()
938 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); in optimizeLogicalImm()