Home
last modified time | relevance | path

Searched refs:DwarfRegNum (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td91 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
93 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
118 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
119 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
120 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
121 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
188 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
223 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>;
224 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>;
225 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td29 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
30 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
31 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
32 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
34 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
35 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
36 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
37 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
38 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
39 def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td49 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
51 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
52 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
53 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
54 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
55 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
56 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
57 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
59 def X8 : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
60 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td128 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
130 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
131 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
132 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
133 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
134 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
135 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
136 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
137 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
39 def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
40 def SP : Ri<14, "sp">, DwarfRegNum<[14]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
173 DwarfRegNum<[!add(I, 32)]>;
179 DwarfRegNum<[!add(I, 32)]>;
182 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
183 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
184 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
185 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
186 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
187 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
188 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86RegisterInfo.td191 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
192 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
193 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
194 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
195 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
196 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
197 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
198 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
211 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
212 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td61 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
62 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
63 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
64 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
65 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
66 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
67 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
68 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
69 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
70 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td72 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
73 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
74 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
75 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
76 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
77 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
78 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
79 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
82 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
83 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td107 def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
113 DwarfRegNum<[Index, -2]>;
219 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
221 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
224 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
225 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
228 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEACC: DwarfRegNum<[99, 111]>;
234 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
236 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DStackMaps.cpp158 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand() local
159 unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
165 DwarfRegNum, Offset); in parseOperand()
239 OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " in print()
249 unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI); in createLiveOutReg() local
251 return LiveOutReg(Reg, DwarfRegNum, Size); in createLiveOutReg()
273 return LHS.DwarfRegNum < RHS.DwarfRegNum; in parseRegisterLiveOutMask()
278 if (I->DwarfRegNum != II->DwarfRegNum) { in parseRegisterLiveOutMask()
539 OS.EmitIntValue(LO.DwarfRegNum, 2); in emitCallsiteEntries()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DStackMaps.h217 unsigned short DwarfRegNum = 0; member
221 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum, in LiveOutReg()
223 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {} in LiveOutReg()
/freebsd-12.1/contrib/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp197 uint64_t DwarfRegNum; in prettyPrintRegisterOp() local
201 DwarfRegNum = Operands[OpNum++]; in prettyPrintRegisterOp()
203 DwarfRegNum = Opcode - DW_OP_breg0; in prettyPrintRegisterOp()
205 DwarfRegNum = Opcode - DW_OP_reg0; in prettyPrintRegisterOp()
207 int LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH); in prettyPrintRegisterOp()
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td34 def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
36 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td81 DwarfRegNum<[I]>;
203 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
208 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
237 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
304 def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>;
314 def C#I : CREG64<I, "c"#I>, DwarfRegNum<[!add(I, 32)]>;
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td27 def R#i : LanaiReg<i, "r"#i>, DwarfRegNum<[i]>;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td34 DwarfRegNum<[!cast<int>(HWEncoding)]> {
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTarget.td364 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
368 class DwarfRegNum<list<int> Numbers> {