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Searched refs:DestRC (Results 1 – 5 of 5) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
41 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
45 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
47 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
49 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
52 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
55 } else if (DestRC == &NVPTX::Float16RegsRegClass) { in copyPhysReg()
58 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) { in copyPhysReg()
60 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
63 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp382 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
387 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
390 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
585 if (DestRC != RC) { in ListScheduleBottomUp()
587 if (!DestRC && !NewDef) in ListScheduleBottomUp()
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
H A DScheduleDAGRRList.cpp1212 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1217 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1220 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1542 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1552 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1554 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1560 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp452 const TargetRegisterClass *DestRC in foldOperand() local
461 if (TRI->isSGPRClass(SrcRC) && TRI->hasVGPRs(DestRC)) { in foldOperand()
482 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
H A DSIInstrInfo.cpp4645 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
4646 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
4780 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
4781 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
4823 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
4841 unsigned NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()