| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | InfoByHwMode.h | 37 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
52 if (M != DefaultMode) in union_modes()
57 V.push_back(DefaultMode); in union_modes()
85 bool hasDefault() const { return hasMode(DefaultMode); } in hasDefault()
89 assert(hasMode(DefaultMode)); in get()
90 Map.insert({Mode, Map.at(DefaultMode)}); in get()
96 if (Mode != DefaultMode && F == Map.end()) in get()
97 F = Map.find(DefaultMode); in get()
104 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
115 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
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| H A D | RegisterBankEmitter.cpp | 88 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
89 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
247 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
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| H A D | InfoByHwMode.cpp | 28 if (Mode == DefaultMode) in getModeName()
65 auto D = Map.find(DefaultMode); in getOrCreateTypeForMode()
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| H A D | CodeGenHwModes.h | 43 enum : unsigned { DefaultMode = 0 }; enumerator
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| H A D | CodeGenHwModes.cpp | 82 return DefaultMode; in getHwModeId()
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| H A D | CodeGenDAGPatterns.cpp | 115 if (DefaultMode == M) { in insert()
137 if (M == DefaultMode || hasMode(M)) in constrain()
139 Map.insert({M, Map.at(DefaultMode)}); in constrain()
748 const TypeSetByHwMode::SetType &LegalTypes = Legal.get(DefaultMode); in expandOverloads()
805 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1619 if (S.get(DefaultMode).empty()) in setDefaultMode()
4208 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4222 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4227 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4229 AppendPattern(P, DefaultMode); in ExpandHwModeBasedTypes()
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| H A D | CodeGenDAGPatterns.h | 227 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isDefaultOnly()
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| H A D | CodeGenRegisters.cpp | 793 RSI.Map.insert({DefaultMode, RI}); in CodeGenRegisterClass()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 286 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
288 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
290 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
292 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
295 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
297 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
299 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
302 def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
304 def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
306 def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 87 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
101 [RV32, RV64, DefaultMode],
116 [RV32, RV64, DefaultMode],
129 [RV32, RV64, DefaultMode],
138 [RV32, RV64, DefaultMode],
151 [RV32, RV64, DefaultMode],
157 [RV32, RV64, DefaultMode],
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIModeRegister.cpp | 131 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon59bb2fbe0111::SIModeRegister
133 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | Target.td | 37 def DefaultMode : HwMode<"">;
|