| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 352 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
357 if (DefRC == SrcRC) in shareSameRegisterFile()
363 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
371 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
376 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
379 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
382 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
387 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
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| H A D | DetectDeadLanes.cpp | 374 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
388 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
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| H A D | PeepholeOptimizer.cpp | 669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1233 unsigned NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
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| H A D | RegisterCoalescer.cpp | 1225 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1237 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1268 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1317 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1319 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1321 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 733 const TargetRegisterClass *DefRC = nullptr; in select() local
735 DefRC = TRI.getRegClass(DefReg); in select()
740 DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); in select()
741 if (!DefRC) { in select()
747 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
748 if (!DefRC) { in select()
756 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 167 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | SIRegisterInfo.cpp | 1359 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
1379 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 559 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 2327 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
2332 unsigned UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1942 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1943 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1944 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
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