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Searched refs:CreateReg (Results 1 – 25 of 52) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrBuilder.h70 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
78 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
86 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixWWMLiveness.cpp344 OtherDef->addOperand(MachineOperand::CreateReg(Reg, false, /*isImp=*/true)); in processThenDef()
378 DefOpnd->getParent()->addOperand(MachineOperand::CreateReg( in processLoopExitDef()
413 Def->addOperand(MachineOperand::CreateReg(Reg, false, /*isImp=*/true)); in processLoopPhiDef()
H A DSIFixupVectorISel.cpp191 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false)); in fixupGlobalSaddr()
194 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
H A DSIFixVGPRCopies.cpp61 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DLiveVariables.cpp247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineInstr.cpp106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); in addImplicitDefUseOperands()
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); in addImplicitDefUseOperands()
1815 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
1882 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
1919 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
H A DLiveDebugVariables.cpp583 MachineOperand MO = MachineOperand::CreateReg(0U, false); in handleDebugValue()
962 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false); in splitLocation()
1214 MachineOperand::CreateReg(/* Reg */ 0, /* isDef */ false, /* isImp */ false, in insertDebugValue()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp785 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in addStackMapLiveVars()
833 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
945 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true)); in selectPatchpoint()
994 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
1000 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
1013 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
1019 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true, in selectPatchpoint()
1047 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
1049 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
1363 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
[all …]
H A DFunctionLoweringInfo.cpp355 unsigned FunctionLoweringInfo::CreateReg(MVT VT) { in CreateReg() function in FunctionLoweringInfo
380 unsigned R = CreateReg(RegisterVT); in CreateRegs()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp220 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
227 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
H A DHexagonHardwareLoops.cpp1910 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true)); in createPreheaderForLoop()
1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
1936 PN->addOperand(MachineOperand::CreateReg(NewPR, false)); in createPreheaderForLoop()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(PPC::X2, in processBlock()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp222 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
251 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h458 MachineOperand::CreateReg(PredReg, false)}};
464 return MachineOperand::CreateReg(CCReg, false);
471 return MachineOperand::CreateReg(ARM::CPSR,
H A DThumb2InstrInfo.cpp517 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
548 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp86 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in ImposeStackOrdering()
92 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in ImposeStackOrdering()
126 MI->addOperand(MachineOperand::CreateReg(TempReg, false)); in ConvertImplicitDefToConstZero()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h239 unsigned CreateReg(MVT VT);
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp197 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anonebdbea530111::MSP430Operand
443 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp54 Callee = MachineOperand::CreateReg(GetCalleeReg(), false); in lowerCall()
H A DCSEInfo.cpp305 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/freebsd-12.1/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1753 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true, in ParseIntelOffsetOfOperator()
1860 return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) : in ParseIntelOperand()
1990 return X86Operand::CreateReg(Reg, Loc, EndLoc); in ParseATTOperand()
2081 X86Operand::CreateReg(RegNo, StartLoc, StartLoc)); in HandleAVX512Operand()
2598 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc); in ParseInstruction()
2610 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in ParseInstruction()
2619 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in ParseInstruction()
2633 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), in ParseInstruction()
2644 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); in ParseInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp189 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon541144770111::AVROperand
373 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp387 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() function in __anon94a376d70211::SparcOperand
829 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); in parseOperand()
889 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); in parseSparcAsmOperand()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1825 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() function in __anon7d8c15f70111::AArch64Operand
1852 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
3441 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
3460 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
3477 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
3492 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4576 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
4739 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
4755 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
4772 Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp430 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() function
886 HexagonOperand::CreateReg(getContext(), Register, Begin, End)); in parseOperand()
904 HexagonOperand::CreateReg(getContext(), Register, Begin, End)); in parseOperand()
916 HexagonOperand::CreateReg(getContext(), Register, Begin, End)); in parseOperand()

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