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Searched refs:CondCode (Results 1 – 25 of 92) sorted by relevance

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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h959 enum CondCode { enum
992 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
998 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
1005 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
1012 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
1018 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
1022 CondCode getSetCCSwappedOperands(CondCode Operation);
1027 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
1032 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
H A DAnalysis.h89 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
93 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
98 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp102 using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
112 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
114 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
229 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
243 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
274 AArch64CC::CondCode Cmp; in modifyCmp()
305 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
309 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
319 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
376 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
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H A DAArch64SpeculationHardening.cpp154 AArch64CC::CondCode &CondCode) const;
156 AArch64CC::CondCode &CondCode, DebugLoc DL) const;
188 AArch64CC::CondCode &CondCode) const { in endsWithCondControlFlow()
213 CondCode = AArch64CC::CondCode(analyzeBranchCondCode[0].getImm()); in endsWithCondControlFlow()
226 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode() argument
235 .addImm(CondCode); in insertTrackingCode()
247 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
249 if (!endsWithCondControlFlow(MBB, TBB, FBB, CondCode)) { in instrumentControlFlow()
256 AArch64CC::CondCode InvCondCode = AArch64CC::getInvertedCondCode(CondCode); in instrumentControlFlow()
268 insertTrackingCode(*SplitEdgeTBB, CondCode, DL); in instrumentControlFlow()
H A DAArch64InstructionSelector.cpp542 AArch64CC::CondCode &CondCode, in changeFCMPPredToAArch64CC() argument
549 CondCode = AArch64CC::EQ; in changeFCMPPredToAArch64CC()
552 CondCode = AArch64CC::GT; in changeFCMPPredToAArch64CC()
555 CondCode = AArch64CC::GE; in changeFCMPPredToAArch64CC()
558 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
561 CondCode = AArch64CC::LS; in changeFCMPPredToAArch64CC()
564 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
568 CondCode = AArch64CC::VC; in changeFCMPPredToAArch64CC()
571 CondCode = AArch64CC::VS; in changeFCMPPredToAArch64CC()
574 CondCode = AArch64CC::EQ; in changeFCMPPredToAArch64CC()
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H A DAArch64ConditionalCompares.cpp164 AArch64CC::CondCode HeadCmpBBCC;
170 AArch64CC::CondCode CmpBBTailCC;
273 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
277 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
H A DAArch64ISelLowering.cpp1325 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { in changeIntCCToAArch64CC()
1354 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC() argument
1362 CondCode = AArch64CC::EQ; in changeFPCCToAArch64CC()
1417 AArch64CC::CondCode &CondCode, in changeFPCCToANDAArch64CC() argument
1447 AArch64CC::CondCode &CondCode, in changeVectorFPCCToAArch64CC() argument
1805 AArch64CC::CondCode RHSCC; in emitConjunctionRec()
2147 AArch64CC::CondCode CC; in LowerXOR()
2250 AArch64CC::CondCode CC; in LowerXALUO()
4941 ISD::CondCode CC; in LowerSELECT()
9641 ISD::CondCode CC;
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/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp38 enum CondCode { enum
134 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
147 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
158 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
213 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in analyzeBranch()
234 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in analyzeBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
407 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in reverseBranchCondition()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.h41 enum CondCode { enum
72 unsigned GetCondBranchFromCond(CondCode CC);
76 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
80 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
88 CondCode getCondFromBranchOpc(unsigned Opc);
91 CondCode getCondFromSETOpc(unsigned Opc);
94 CondCode getCondFromCMovOpc(unsigned Opc);
98 CondCode GetOppositeBranchCondition(CondCode CC);
101 unsigned getVPCMPImmForCond(ISD::CondCode CC);
H A DX86CondBrFolding.cpp96 X86::CondCode BranchCode;
158 X86::CondCode CC = PredMBBInfo->BranchCode; in findPath()
256 X86::CondCode CC = MBBInfo->BranchCode; in fixupModifiedCond()
287 X86::CondCode CC; in optimizeCondBr()
315 X86::CondCode NewCC; in optimizeCondBr()
490 X86::CondCode CC; in analyzeMBB()
H A DX86FlagsCopyLowering.cpp111 DebugLoc TestLoc, X86::CondCode Cond);
115 X86::CondCode Cond, CondRegArray &CondRegs);
733 X86::CondCode Cond = X86::getCondFromSETOpc(MI.getOpcode()); in collectCondsInRegs()
751 DebugLoc TestLoc, X86::CondCode Cond) { in promoteCondToReg()
763 DebugLoc TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg()
791 X86::CondCode Cond; in rewriteArithmetic()
845 X86::CondCode Cond = X86::getCondFromCMovOpc(CMovI.getOpcode()); in rewriteCMov()
870 X86::CondCode Cond = X86::getCondFromBranchOpc(JmpI.getOpcode()); in rewriteCondJmp()
1029 X86::CondCode Cond = X86::getCondFromSETOpc(SetCCI.getOpcode()); in rewriteSetCC()
H A DX86CmovConversion.cpp284 X86::CondCode FirstCC, FirstOppCC, MemOpCC; in collectCmovCandidates()
294 X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode()); in collectCmovCandidates()
655 X86::CondCode CC = X86::CondCode(X86::getCondFromCMovOpc(MI.getOpcode())); in convertCmovInstsToBranches()
656 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC); in convertCmovInstsToBranches()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiCondCode.h10 enum CondCode { enum
34 inline static StringRef lanaiCondCodeToString(LPCC::CondCode CC) { in lanaiCondCodeToString()
73 inline static CondCode suffixToLanaiCondCode(StringRef S) { in suffixToLanaiCondCode()
74 return StringSwitch<CondCode>(S) in suffixToLanaiCondCode()
H A DLanaiInstrInfo.cpp124 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) { in getOppositeCondition()
352 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4> in optimizeCompareInstr()
372 LPCC::CondCode CC; in optimizeCompareInstr()
373 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
376 LPCC::CondCode NewCC = getOppositeCondition(CC); in optimizeCompareInstr()
523 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
525 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode))); in optimizeSelect()
527 NewMI.addImm(CondCode); in optimizeSelect()
626 LPCC::CondCode BranchCond = in analyzeBranch()
652 LPCC::CondCode BranchCond = in reverseBranchCondition()
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/freebsd-12.1/contrib/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp318 unsigned CondCode; in parseJccInstruction() local
320 CondCode = MSP430CC::COND_NE; in parseJccInstruction()
322 CondCode = MSP430CC::COND_E; in parseJccInstruction()
324 CondCode = MSP430CC::COND_LO; in parseJccInstruction()
326 CondCode = MSP430CC::COND_HS; in parseJccInstruction()
328 CondCode = MSP430CC::COND_N; in parseJccInstruction()
330 CondCode = MSP430CC::COND_GE; in parseJccInstruction()
332 CondCode = MSP430CC::COND_L; in parseJccInstruction()
334 CondCode = MSP430CC::COND_NONE; in parseJccInstruction()
338 if (CondCode == (unsigned)MSP430CC::COND_NONE) in parseJccInstruction()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h193 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
214 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
236 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/InstPrinter/
H A DLanaiInstPrinter.cpp287 LPCC::CondCode CC = in printCCOperand()
288 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printCCOperand()
298 LPCC::CondCode CC = in printPredicateOperand()
299 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printPredicateOperand()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td577 class CondCode; // ISD::CondCode enums
578 def SETOEQ : CondCode; def SETOGT : CondCode;
579 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
580 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
581 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
582 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
584 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
585 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
/freebsd-12.1/contrib/llvm/lib/Target/ARC/InstPrinter/
H A DARCInstPrinter.cpp55 static const char *ARCCondCodeToString(ARCCC::CondCode CC) { in ARCCondCodeToString()
172 O << ARCCondCodeToString((ARCCC::CondCode)Op.getImm()); in printPredicateOperand()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp90 static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC) { in GetOppositeBranchCondition()
341 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
H A DARCISelLowering.cpp42 static ARCCC::CondCode ISDCCtoARCCC(ISD::CondCode isdCC) { in ISDCCtoARCCC()
167 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
171 ARCCC::CondCode ArcCC = ISDCCtoARCCC(CC); in LowerSELECT_CC()
200 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
205 ARCCC::CondCode arcCC = ISDCCtoARCCC(CC); in LowerBR_CC()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp1052 LPCC::CondCode CondCode = in splitMnemonic() local
1054 if (CondCode != LPCC::UNKNOWN) { in splitMnemonic()
1058 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc)); in splitMnemonic()
1072 LPCC::CondCode CondCode = LPCC::suffixToLanaiCondCode(Mnemonic); in splitMnemonic() local
1073 if (CondCode != LPCC::UNKNOWN) { in splitMnemonic()
1087 MCConstantExpr::create(CondCode, getContext()), NameLoc, NameLoc)); in splitMnemonic()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInfo.h25 enum CondCode { enum
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DAnalysis.cpp161 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
183 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
198 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()

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