1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 4 * 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Ken Hornstein and John Kohl. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /** 34 * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer 35 * chip, used on Gravis UltraSound MAX cards. 36 * 37 * Block diagram: 38 * +----------------------------------------------------+ 39 * | | 40 * | +----------------------------------------------+ | 41 * | |mixed in +-+ | | 42 * | +------------>--| | | | 43 * | mic in | | | | 44 * Mic --+-->| --------- GAIN ->-| | | | 45 * | | AUX 1 in |M| | | 46 * GF1 --)-->| -------------+-->-|U| | | 47 * | | Line in | |X|---- GAIN ----------+ | | 48 * Line --)-->| ---------+---)-->-| | | | | 49 * | | | | | | | | | 50 * | | | | +-+ ADC | | 51 * | | | | | | | 52 * | | | | | | | 53 * | | | +--- L/M --\ | | | AMP--> 54 * | | | \ | | | | 55 * | | | \ | | | | 56 * | | +---- L/M -------O-->--+--------)-------+-|--+-> line 57 * | | mono in /| | | | 58 * +---|-->------------ L/M -----/ | | | | 59 * | AUX 2 in | | | | 60 * CD --------|-->------------ L/M -------+ L/M | | 61 * | | v | 62 * | | | | 63 * | DAC | | 64 * | | | | 65 * +----------------------------------------------------+ 66 * | | 67 * | | 68 * v v 69 * Pc BUS (DISK) ??? 70 * 71 * Documentation for this chip can be found at: 72 * http://www.cirrus.com/products/overviews/cs4231.html 73 */ 74 75 /* 76 * This file was merged from two header files.(ad1848reg.h and cs4231reg.h) 77 * And the suffix AD1848 and SP was changed to CS4231 and CS respectively. 78 */ 79 /* CS4231 direct registers */ 80 #define CS4231_IADDR 0x00 81 #define CS4231_IDATA 0x01 82 #define CS4231_STATUS 0x02 83 #define CS4231_PIO 0x03 84 85 /* Index address register */ 86 #define CS_IN_INIT 0x80 87 #define MODE_CHANGE_ENABLE 0x40 88 #define TRANSFER_DISABLE 0x20 89 #define ADDRESS_MASK 0xe0 90 91 /* Status bits */ 92 #define INTERRUPT_STATUS 0x01 93 #define PLAYBACK_READY 0x02 94 #define PLAYBACK_LEFT 0x04 95 /* pbright is not left */ 96 #define PLAYBACK_UPPER 0x08 97 /* bplower is not upper */ 98 #define SAMPLE_ERROR 0x10 99 #define CAPTURE_READY 0x20 100 #define CAPTURE_LEFT 0x40 101 /* cpright is not left */ 102 #define CAPTURE_UPPER 0x80 103 /* cplower is not upper */ 104 105 /* CS4231 indirect mapped registers */ 106 #define CS_LEFT_INPUT_CONTROL 0x00 107 #define CS_RIGHT_INPUT_CONTROL 0x01 108 #define CS_LEFT_AUX1_CONTROL 0x02 109 #define CS_RIGHT_AUX1_CONTROL 0x03 110 #define CS_LEFT_AUX2_CONTROL 0x04 111 #define CS_RIGHT_AUX2_CONTROL 0x05 112 #define CS_LEFT_OUTPUT_CONTROL 0x06 113 #define CS_RIGHT_OUTPUT_CONTROL 0x07 114 #define CS_CLOCK_DATA_FORMAT 0x08 115 #define CS_INTERFACE_CONFIG 0x09 116 #define CS_PIN_CONTROL 0x0a 117 #define CS_TEST_AND_INIT 0x0b 118 #define CS_MISC_INFO 0x0c 119 #define CS_DIGITAL_MIX 0x0d 120 #define CS_UPPER_BASE_COUNT 0x0e 121 #define CS_LOWER_BASE_COUNT 0x0f 122 /* CS4231/AD1845 mode2 registers; added to AD1848 registers */ 123 #define CS_ALT_FEATURE1 0x10 124 #define CS_ALT_FEATURE2 0x11 125 #define CS_LEFT_LINE_CONTROL 0x12 126 #define CS_RIGHT_LINE_CONTROL 0x13 127 #define CS_TIMER_LOW 0x14 128 #define CS_TIMER_HIGH 0x15 129 #define CS_UPPER_FREQUENCY_SEL 0x16 130 #define CS_LOWER_FREQUENCY_SEL 0x17 131 #define CS_IRQ_STATUS 0x18 132 #define CS_VERSION_ID 0x19 133 #define CS_MONO_IO_CONTROL 0x1a 134 #define CS_POWERDOWN_CONTROL 0x1b 135 #define CS_REC_FORMAT 0x1c 136 #define CS_XTAL_SELECT 0x1d 137 #define CS_UPPER_REC_CNT 0x1e 138 #define CS_LOWER_REC_CNT 0x1f 139 #define CS_REG_NONE 0xff 140 141 #define CS_IN_MASK 0x2f 142 #define CS_IN_LINE 0x00 143 #define CS_IN_AUX1 0x40 144 #define CS_IN_MIC 0x80 145 #define CS_IN_DAC 0xc0 146 #define CS_MIC_GAIN_ENABLE 0x20 147 #define CS_IN_GAIN_MASK 0xf0 148 149 /* ADC input control - registers I0 (channel 1,left); I1 (channel 1,right) */ 150 #define ADC_INPUT_ATTEN_BITS 0x0f 151 #define ADC_INPUT_GAIN_ENABLE 0x20 152 153 /* Aux input control - registers I2 (channel 1,left); I3 (channel 1,right) 154 I4 (channel 2,left); I5 (channel 2,right) */ 155 #define AUX_INPUT_ATTEN_BITS 0x1f 156 #define AUX_INPUT_ATTEN_MASK 0xe0 157 #define AUX_INPUT_MUTE 0x80 158 159 /* Output bits - registers I6,I7*/ 160 #define OUTPUT_MUTE 0x80 161 #define OUTPUT_ATTEN_BITS 0x3f 162 #define OUTPUT_ATTEN_MASK (~OUTPUT_ATTEN_BITS & 0xff) 163 164 /* Clock and Data format reg bits (some also Capture Data format) - reg I8 */ 165 #define CS_CLOCK_DATA_FORMAT_MASK 0x0f 166 #define CLOCK_XTAL1 0x00 167 #define CLOCK_XTAL2 0x01 168 #define CLOCK_FREQ_MASK 0xf1 169 #define CS_AFMT_STEREO 0x10 170 #define CS_AFMT_U8 0x00 171 #define CS_AFMT_MU_LAW 0x20 172 #define CS_AFMT_S16_LE 0x40 173 #define CS_AFMT_A_LAW 0x60 174 #define CS_AFMT_IMA_ADPCM 0xa0 175 #define CS_AFMT_S16_BE 0xc0 176 177 /* Interface Configuration reg bits - register I9 */ 178 #define PLAYBACK_ENABLE 0x01 179 #define CAPTURE_ENABLE 0x02 180 #define DUAL_DMA 0x00 181 #define SINGLE_DMA 0x04 182 #define AUTO_CAL_ENABLE 0x08 183 #define PLAYBACK_PIO_ENABLE 0x40 184 #define CAPTURE_PIO_ENABLE 0x80 185 186 /* Pin control bits - register I10 */ 187 #define INTERRUPT_ENABLE 0x02 188 #define XCTL0_ENABLE 0x40 189 #define XCTL1_ENABLE 0x80 190 191 /* Test and init reg bits - register I11 (read-only) */ 192 #define OVERRANGE_LEFT_MASK 0xfc 193 #define OVERRANGE_RIGHT_MASK 0xf3 194 #define DATA_REQUEST_STATUS 0x10 195 #define AUTO_CAL_IN_PROG 0x20 196 #define PLAYBACK_UNDERRUN 0x40 197 #define CAPTURE_OVERRUN 0x80 198 199 /* Miscellaneous Control reg bits - register I12 */ 200 #define CS_ID_MASK 0x70 201 #define CS_MODE2 0x40 202 #define CS_CODEC_ID_MASK 0x0f 203 204 /* Digital Mix Control reg bits - register I13 */ 205 #define DIGITAL_MIX1_ENABLE 0x01 206 #define MIX_ATTEN_MASK 0x03 207 208 /* Alternate Feature Enable I - register I16 */ 209 #define CS_DAC_ZERO 0x01 210 #define CS_PMC_ENABLE 0x10 211 #define CS_CMC_ENABLE 0x20 212 #define CS_OUTPUT_LVL 0x80 213 214 /* Alternate Feature Enable II - register I17 */ 215 #define CS_HPF_ENABLE 0x01 216 #define DUAL_XTAL_ENABLE 0x02 217 218 /* alternate feature status(I24) */ 219 #define CS_AFS_TI 0x40 /* timer interrupt */ 220 #define CS_AFS_CI 0x20 /* capture interrupt */ 221 #define CS_AFS_PI 0x10 /* playback interrupt */ 222 #define CS_AFS_CU 0x08 /* capture underrun */ 223 #define CS_AFS_CO 0x04 /* capture overrun */ 224 #define CS_AFS_PO 0x02 /* playback overrun */ 225 #define CS_AFS_PU 0x01 /* playback underrun */ 226 227 /* Version - register I25 */ 228 #define CS_VERSION_NUMBER 0xe0 229 #define CS_VERSION_CHIPID 0x07 230 231 /* Miscellaneous Control reg bits */ 232 #define CS_MODE2 0x40 233 234 #define MONO_INPUT_ATTEN_BITS 0x0f 235 #define MONO_INPUT_ATTEN_MASK 0xf0 236 #define MONO_OUTPUT_MUTE 0x40 237 #define MONO_INPUT_MUTE 0x80 238 #define MONO_INPUT_MUTE_MASK 0x7f 239 240 #define LINE_INPUT_ATTEN_BITS 0x1f 241 #define LINE_INPUT_ATTEN_MASK 0xe0 242 #define LINE_INPUT_MUTE 0x80 243 #define LINE_INPUT_MUTE_MASK 0x7f 244