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Searched refs:CSR_READ_4 (Results 1 – 25 of 90) sorted by relevance

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/freebsd-12.1/sys/arm/amlogic/aml8726/
H A Daml8726_rtc.c125 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
135 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_start_transfer()
143 if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) ) in aml8726_rtc_start_transfer()
151 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_start_transfer()
163 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_sclk_pulse()
200 (CSR_READ_4(sc, AML_RTC_0_REG) & ~AML_RTC_SEN)); in aml8726_rtc_send_addr()
287 if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) ) in aml8726_rtc_initialize()
303 ((CSR_READ_4(sc, AML_RTC_0_REG) & 0xffffff) | in aml8726_rtc_initialize()
307 while ((CSR_READ_4(sc, AML_RTC_0_REG) & AML_RTC_ABSY) != 0) in aml8726_rtc_initialize()
339 previous = CSR_READ_4(sc, AML_RTC_2_REG); in aml8726_rtc_check_xo()
[all …]
H A Daml8726_i2c.c86 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
193 (CSR_READ_4(sc, AML_I2C_CTRL_REG) | AML_I2C_MANUAL_SDA_O | in aml8726_iic_reset()
209 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SCL_I); in aml8726_iic_getscl()
217 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SDA_I); in aml8726_iic_getsda()
227 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) & in aml8726_iic_setscl()
241 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) & in aml8726_iic_setsda()
H A Daml8726_timer.c130 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
138 return CSR_READ_4(sc, AML_TIMER_E_REG); in aml8726_get_timecount()
153 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | in aml8726_hardclock()
197 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) | in aml8726_timer_start()
214 (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN)); in aml8726_timer_stop()
257 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & in aml8726_timer_attach()
266 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN)); in aml8726_timer_attach()
H A Daml8726_gpio.c87 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[reg], 0) macro
223 if ((CSR_READ_4(sc, AML_GPIO_OE_N_REG) & mask) == 0) { in aml8726_gpio_pin_getflags()
248 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask)); in aml8726_gpio_pin_setflags()
252 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask)); in aml8726_gpio_pin_setflags()
281 ((CSR_READ_4(sc, AML_GPIO_OUT_REG) & ~mask) | (value << pin))); in aml8726_gpio_pin_set()
298 *value = (CSR_READ_4(sc, AML_GPIO_IN_REG) & mask) ? 1 : 0; in aml8726_gpio_pin_get()
324 CSR_READ_4(sc, AML_GPIO_OUT_REG) ^ mask); in aml8726_gpio_pin_toggle()
H A Daml8726_usb_phy-m6.c100 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
227 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
256 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
293 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
302 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG); in aml8726_usb_phy_attach()
312 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG); in aml8726_usb_phy_attach()
377 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_detach()
H A Daml8726_rng.c67 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
75 rn[0] = CSR_READ_4(sc, AML_RNG_0_REG); in aml8726_rng_harvest()
76 rn[1] = CSR_READ_4(sc, AML_RNG_1_REG); in aml8726_rng_harvest()
H A Daml8726_pic.c111 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
227 value = CSR_READ_4(aml8726_pic_sc, AML_PIC_STAT_REG(irq)); in arm_get_next_irq()
252 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_mask_irq()
271 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_unmask_irq()
H A Daml8726_usb_phy-m3.c104 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
244 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
329 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
338 value = CSR_READ_4(sc, AML_USB_PHY_MISC_A_REG); in aml8726_usb_phy_attach()
347 value = CSR_READ_4(sc, AML_USB_PHY_MISC_B_REG); in aml8726_usb_phy_attach()
387 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_detach()
H A Daml8726_sdxc-m8.c231 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_engage_dma()
255 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_engage_dma()
278 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_disengage_dma()
296 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_disengage_dma()
359 ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG); in aml8726_sdxc_start_command()
530 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) & in aml8726_sdxc_timeout()
545 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_busy_check()
577 isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG); in aml8726_sdxc_intr()
578 sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG); in aml8726_sdxc_intr()
579 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_intr()
[all …]
H A Daml8726_wdt.c100 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
128 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & in aml8726_wdt_watchdog()
149 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN | in aml8726_wdt_intr()
240 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN | in aml8726_wdt_attach()
/freebsd-12.1/sys/mips/ingenic/
H A Djz4780_clock.c579 *val = CSR_READ_4(sc, addr); in jz4780_clock_read_4()
591 val = CSR_READ_4(sc, addr); in jz4780_clock_modify_4()
687 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ohci_enable()
718 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
723 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ehci_enable()
743 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
747 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
752 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
758 reg = CSR_READ_4(sc, JZ_SRBC); in jz4780_ehci_enable()
801 reg = CSR_READ_4(sc, JZ_USBRDT); in jz4780_otg_enable()
[all …]
H A Djz4780_efuse.c75 #define CSR_READ_4(sc, reg) \ macro
104 while ((CSR_READ_4(sc, JZ_EFUSTATE) & JZ_EFUSE_RD_DONE) == 0) in jz4780_efuse_read_chunk()
111 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
118 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
H A Djz4780_gpio.c110 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
240 val = CSR_READ_4(sc, JZ_GPIO_INT); in jz4780_gpio_pin_probe()
243 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
249 val = CSR_READ_4(sc, JZ_GPIO_PAT0); in jz4780_gpio_pin_probe()
260 val = CSR_READ_4(sc, JZ_GPIO_MASK); in jz4780_gpio_pin_probe()
263 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
269 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
277 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
524 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_get()
547 data = CSR_READ_4(sc, JZ_GPIO_PIN); in jz4780_gpio_pin_toggle()
[all …]
/freebsd-12.1/sys/dev/bge/
H A Dif_bge.c676 CSR_READ_4(sc, off); in bge_writembx()
1054 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
1120 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1171 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1174 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
2524 dmactl = CSR_READ_4(sc, rdmareg); in bge_blockinit()
4227 val = CSR_READ_4(sc, BGE_MAC_MODE); in bge_reset()
4286 val = CSR_READ_4(sc, 0x7C00); in bge_reset()
5560 mode = CSR_READ_4(sc, BGE_TX_MODE); in bge_init_locked()
5750 if (CSR_READ_4(sc, BGE_MAC_STS) & in bge_ifmedia_sts()
[all …]
/freebsd-12.1/sys/dev/et/
H A Dif_et.c442 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
456 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
487 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
542 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
547 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
1193 status = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1575 pktfilt = CSR_READ_4(sc, ET_PKTFILT); in et_setmulti()
2281 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); in et_txeof()
[all …]
/freebsd-12.1/sys/dev/dc/
H A Ddcphy.c77 CSR_READ_4(sc, reg) | x)
81 CSR_READ_4(sc, reg) & ~x)
210 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
265 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
311 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
315 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
368 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
372 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
/freebsd-12.1/sys/dev/alc/
H A Dif_alc.c306 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
333 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
371 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
397 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
492 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
523 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
720 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
747 CSR_READ_4(sc, ALC_WOL_CFG); in alc_get_macaddr_813x()
771 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
808 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
[all …]
/freebsd-12.1/sys/dev/nge/
H A Dif_nge.c250 CSR_READ_4(sc, reg) | (x))
254 CSR_READ_4(sc, reg) & ~(x))
268 CSR_READ_4(sc, NGE_CSR); in nge_delay()
392 val = CSR_READ_4(sc, NGE_MEAR); in nge_mii_bitbang_read()
458 return (CSR_READ_4(sc, reg)); in nge_miibus_readreg()
592 reg = CSR_READ_4(sc, NGE_CFG); in nge_miibus_statchg()
607 reg = CSR_READ_4(sc, NGE_CSR); in nge_miibus_statchg()
645 reg = CSR_READ_4(sc, NGE_CSR); in nge_miibus_statchg()
786 v = CSR_READ_4(sc, NGE_CFG); in nge_reset()
2438 reg = CSR_READ_4(sc, NGE_CSR); in nge_stop_mac()
[all …]
/freebsd-12.1/sys/dev/bfe/
H A Dif_bfe.c892 CSR_READ_4(sc, reg); in bfe_clear_stats()
894 CSR_READ_4(sc, reg); in bfe_clear_stats()
918 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
1026 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_disable()
1043 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1055 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1060 CSR_READ_4(sc, BFE_SBTMSLOW); in bfe_core_reset()
1093 val = CSR_READ_4(sc, BFE_RXCONF); in bfe_set_rx_mode()
1262 *val++ = CSR_READ_4(sc, reg); in bfe_stats_update()
1264 *val++ = CSR_READ_4(sc, reg); in bfe_stats_update()
[all …]
/freebsd-12.1/sys/dev/jme/
H A Dif_jme.c361 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
386 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
494 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
495 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
1608 pmcs = CSR_READ_4(sc, JME_PMCS); in jme_setwol()
2719 CSR_READ_4(sc, JME_GHC); in jme_reset()
2735 ghc = CSR_READ_4(sc, JME_GHC); in jme_reset()
2741 CSR_READ_4(sc, JME_GPREG1); in jme_reset()
2748 CSR_READ_4(sc, JME_GHC); in jme_reset()
2886 reg = CSR_READ_4(sc, JME_PMCS); in jme_init_locked()
[all …]
/freebsd-12.1/sys/dev/sis/
H A Dif_sis.c198 CSR_READ_4(sc, reg) | (x))
202 CSR_READ_4(sc, reg) & ~(x))
231 CSR_READ_4(sc, SIS_CSR); in sis_delay()
418 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
448 val = CSR_READ_4(sc, SIS_EECTL); in sis_mii_bitbang_read()
489 if (!CSR_READ_4(sc, NS_BMSR)) in sis_miibus_readreg()
712 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_ns()
765 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_ns()
787 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_sis()
828 CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_rxfilter_sis()
[all …]
/freebsd-12.1/sys/dev/bwi/
H A Dbwimac.c200 return CSR_READ_4(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
470 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
476 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
571 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_test()
1451 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_start()
1452 CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_start()
1470 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_stop()
1500 CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_config_ps()
1565 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_get_property()
1577 val = CSR_READ_4(sc, BWI_STATE_HI); in bwi_mac_get_property()
[all …]
/freebsd-12.1/sys/dev/stge/
H A Dif_stge.c1397 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link_task()
1418 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1876 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1882 CSR_READ_4(sc, STGE_OctetXmtdOk); in stge_stats_update()
1887 CSR_READ_4(sc, STGE_LateCollisions) + in stge_stats_update()
1888 CSR_READ_4(sc, STGE_MultiColFrames) + in stge_stats_update()
1889 CSR_READ_4(sc, STGE_SingleColFrames)); in stge_stats_update()
1911 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_reset()
1949 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_reset()
2146 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_init_locked()
[all …]
/freebsd-12.1/sys/dev/altera/atse/
H A Dif_atse.c182 #define CSR_READ_4(sc, reg) \ macro
407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
456 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_rxfilter_locked()
756 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
798 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
836 val4 = CSR_READ_4(sc, TX_CMD_STAT); in atse_reset()
840 val4 = CSR_READ_4(sc, RX_CMD_STAT); in atse_reset()
846 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
864 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
[all …]
/freebsd-12.1/sys/dev/ale/
H A Dif_ale.c218 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
245 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
295 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
368 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
396 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
397 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
1530 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_setwol()
2089 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_mac_config()
2671 CSR_READ_4(sc, ALE_WOL_CFG); in ale_init_locked()
2887 reg = CSR_READ_4(sc, ALE_TXQ_CFG); in ale_stop()
[all …]

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