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Searched refs:CSR_READ_2 (Results 1 – 25 of 63) sorted by relevance

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/freebsd-12.1/sys/dev/sn/
H A Dif_sn.c185 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; in sn_attach()
191 i = CSR_READ_2(sc, CONFIG_REG_W); in sn_attach()
202 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); in sn_attach()
300 flags = CSR_READ_2(sc, CONFIG_REG_W); in sninit_locked()
881 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); in snintr_locked()
899 tx_status = CSR_READ_2(sc, DATA_REG_W); in snintr_locked()
955 card_stats = CSR_READ_2(sc, COUNTER_REG_W); in snintr_locked()
1015 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); in snread()
1037 status = CSR_READ_2(sc, DATA_REG_W); in snread()
1297 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); in sn_probe()
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H A Dif_snreg.h405 #define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \
406 CSR_READ_2(sc, RECV_CONTROL_REG_W); \
407 CSR_READ_2(sc, RECV_CONTROL_REG_W); }
H A Dif_snvar.h61 #define CSR_READ_2(sc, off) (bus_read_2((sc)->port_res, off)) macro
/freebsd-12.1/sys/dev/vte/
H A Dif_vte.c365 mid = CSR_READ_2(sc, VTE_MID0L); in vte_get_macaddr()
368 mid = CSR_READ_2(sc, VTE_MID0M); in vte_get_macaddr()
371 mid = CSR_READ_2(sc, VTE_MID0H); in vte_get_macaddr()
414 CSR_READ_2(sc, VTE_MACID)); in vte_attach()
1240 mcr = CSR_READ_2(sc, VTE_MCR0); in vte_mac_config()
1266 CSR_READ_2(sc, VTE_CNT_MECNT0); in vte_stats_clear()
1267 CSR_READ_2(sc, VTE_CNT_MECNT1); in vte_stats_clear()
1272 CSR_READ_2(sc, VTE_CNT_PAUSE); in vte_stats_clear()
1285 CSR_READ_2(sc, VTE_MECISR); in vte_stats_update()
1786 CSR_READ_2(sc, VTE_MISR); in vte_stop()
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H A Dif_vtevar.h153 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-12.1/sys/dev/bm/
H A Dif_bm.c190 reg = CSR_READ_2(sc, BM_MII_CSR); in bm_mii_bitbang_read()
223 reg = CSR_READ_2(sc, BM_TX_CONFIG); in bm_miibus_statchg()
972 reg = CSR_READ_2(sc, BM_RX_CONFIG); in bm_setladrf()
1002 reg = CSR_READ_2(sc, BM_TX_RESET); in bm_chip_setup()
1010 reg = CSR_READ_2(sc, BM_TX_IFC); in bm_chip_setup()
1014 CSR_READ_2(sc, BM_TX_PEAKCNT); in bm_chip_setup()
1146 CSR_READ_2(sc, BM_STATUS); in bm_init_locked()
1204 CSR_READ_2(sc, BM_TX_NCCNT) + CSR_READ_2(sc, BM_TX_FCCNT) + in bm_tick()
1205 CSR_READ_2(sc, BM_TX_EXCNT) + CSR_READ_2(sc, BM_TX_LTCNT)); in bm_tick()
1208 CSR_READ_2(sc, BM_RX_LECNT) + CSR_READ_2(sc, BM_RX_AECNT) + in bm_tick()
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H A Dif_bmreg.h166 #define CSR_READ_2(sc, reg) \ macro
/freebsd-12.1/sys/dev/ep/
H A Dif_ep.c151 (*result) = CSR_READ_2(sc, EP_W0_EEPROM_DATA); in ep_get_e()
232 config = CSR_READ_2(sc, EP_W0_CONFIG_CTRL); in ep_get_media()
524 if (CSR_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) { in epstart_locked()
602 if (sc->gone || CSR_READ_2(sc, EP_STATUS) == 0xffff) in ep_intr_locked()
622 CSR_READ_2(sc, EP_W1_FREE_TX); in ep_intr_locked()
631 CSR_READ_2(sc, EP_W4_FIFO_DIAG)); in ep_intr_locked()
695 CSR_READ_2(sc, EP_W1_FREE_TX); in ep_intr_locked()
721 status = CSR_READ_2(sc, EP_W1_RX_STATUS); in epread()
799 status = CSR_READ_2(sc, EP_W1_RX_STATUS); in epread()
884 j = CSR_READ_2(sc, EP_W0_ADDRESS_CFG) & 0x3fff; in ep_ifmedia_upd()
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H A Dif_epreg.h64 #define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
320 #define EP_BUSY_WAIT(sc) while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS)
337 ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \
/freebsd-12.1/sys/dev/vx/
H A Dif_vx.c189 x = CSR_READ_2(sc, VX_W0_EEPROM_DATA); in vx_attach()
300 sc->vx_connectors = CSR_READ_2(sc, VX_W3_RESET_OPT) & 0x7f; in vx_getlink()
476 if (CSR_READ_2(sc, VX_W1_FREE_TX) < len + pad + 4) { in vx_start_locked()
480 if (CSR_READ_2(sc, VX_W1_FREE_TX) < len + pad + 4) { in vx_start_locked()
524 if ((CSR_READ_2(sc, VX_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) { in vx_start_locked()
527 if ((CSR_READ_2(sc, VX_STATUS) & S_INTR_LATCH) == 0) { in vx_start_locked()
571 fifost = CSR_READ_2(sc, VX_W4_FIFO_DIAG); in vx_status()
652 status = CSR_READ_2(sc, VX_STATUS); in vx_intr()
700 len = CSR_READ_2(sc, VX_W1_RX_STATUS); in vx_read()
792 len = CSR_READ_2(sc, VX_W1_RX_STATUS); in vx_read()
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H A Dif_vxvar.h71 #define CSR_READ_2(sc, reg) \ macro
/freebsd-12.1/sys/dev/ste/
H A Dif_ste.c285 cfg = CSR_READ_2(sc, STE_MACCTL0); in ste_miibus_statchg()
491 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_poll_locked()
523 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_intr()
813 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); in ste_stats_clear()
814 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); in ste_stats_clear()
815 CSR_READ_2(sc, STE_STAT_RX_FRAMES); in ste_stats_clear()
822 CSR_READ_2(sc, STE_STAT_TX_FRAMES); in ste_stats_clear()
1649 val = CSR_READ_2(sc, STE_MACCTL1); in ste_stop()
1662 CSR_READ_2(sc, STE_ISR_ACK); in ste_stop()
1727 mac = CSR_READ_2(sc, STE_MACCTL1); in ste_restart_tx()
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/freebsd-12.1/sys/dev/an/
H A Dif_an.c851 id = CSR_READ_2(sc, AN_RX_FID); in an_rxeof()
1216 if (CSR_READ_2(sc, AN_LINKSTAT(sc->mpi350)) in an_intr()
1328 CSR_READ_2(sc, AN_RESP0(sc->mpi350)); in an_cmd()
1329 CSR_READ_2(sc, AN_RESP1(sc->mpi350)); in an_cmd()
1330 CSR_READ_2(sc, AN_RESP2(sc->mpi350)); in an_cmd()
1331 s = CSR_READ_2(sc, AN_STATUS(sc->mpi350)); in an_cmd()
1411 len = CSR_READ_2(sc, AN_DATA1); in an_read_record()
1425 *ptr++ = CSR_READ_2(sc, AN_DATA1); in an_read_record()
1530 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) in an_write_record()
1677 *ptr++ = CSR_READ_2(sc, AN_DATA1); in an_read_data()
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/freebsd-12.1/sys/dev/ex/
H A Dif_ex.c544 i = CSR_READ_2(sc, IO_PORT_REG); in ex_start_locked()
558 CSR_READ_2(sc, IO_PORT_REG); in ex_start_locked()
684 if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit)) in ex_tx_intr()
687 tx_status = CSR_READ_2(sc, IO_PORT_REG); in ex_tx_intr()
688 sc->tx_head = CSR_READ_2(sc, IO_PORT_REG); in ex_tx_intr()
734 while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) { in ex_rx_intr()
736 rx_status = CSR_READ_2(sc, IO_PORT_REG); in ex_rx_intr()
737 sc->rx_head = CSR_READ_2(sc, IO_PORT_REG); in ex_rx_intr()
738 QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG); in ex_rx_intr()
925 CSR_READ_2(sc, IO_PORT_REG); in ex_setmulti()
/freebsd-12.1/sys/dev/vge/
H A Dif_vgevar.h228 #define CSR_READ_2(sc, reg) \ macro
236 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
243 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-12.1/sys/dev/stge/
H A Dif_stge.c407 *data = CSR_READ_2(sc, STGE_EepromData); in stge_read_eeprom()
544 v = CSR_READ_2(sc, STGE_StationAddress0); in stge_attach()
547 v = CSR_READ_2(sc, STGE_StationAddress1); in stge_attach()
550 v = CSR_READ_2(sc, STGE_StationAddress2); in stge_attach()
1469 status = CSR_READ_2(sc, STGE_IntStatus); in stge_intr()
1475 status = CSR_READ_2(sc, STGE_IntStatusAck); in stge_intr()
1800 status = CSR_READ_2(sc, STGE_IntStatus); in stge_poll()
1892 CSR_READ_2(sc, STGE_FramesAbortXSColls) + in stge_stats_update()
1893 CSR_READ_2(sc, STGE_FramesWEXDeferal)); in stge_stats_update()
2496 mode = CSR_READ_2(sc, STGE_ReceiveMode); in stge_set_filter()
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/freebsd-12.1/sys/dev/wi/
H A Dif_wi_pci.c213 (CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) in wi_pci_attach()
224 reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF); in wi_pci_attach()
H A Dif_wi.c576 status = CSR_READ_2(sc, WI_EVENT_STAT); in wi_intr()
1267 fid = CSR_READ_2(sc, WI_RX_FID); in wi_rx_intr()
1367 fid = CSR_READ_2(sc, WI_TX_CMP_FID); in wi_tx_ex_intr()
1409 fid = CSR_READ_2(sc, WI_ALLOC_FID); in wi_tx_intr()
1442 fid = CSR_READ_2(sc, WI_INFO_FID); in wi_info_intr()
1762 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) in wi_cmd()
1787 s = CSR_READ_2(sc, WI_EVENT_STAT); in wi_cmd()
1790 s = CSR_READ_2(sc, WI_STATUS); in wi_cmd()
1819 status = CSR_READ_2(sc, WI_OFF0); in wi_seek_bap()
1918 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC) in wi_alloc_fid()
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/freebsd-12.1/sys/dev/bwi/
H A Dbwirf.c223 return CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_read()
254 val = CSR_READ_2(sc, BWI_RF_DATA_HI); in bwi_rf_attach()
258 val |= CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_attach()
785 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL); in bwi_rf_init_bcm2050()
822 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); in bwi_rf_init_bcm2050()
1283 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_lo_update_11g()
1285 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_lo_update_11g()
1664 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_calc_nrssi_slope_11b()
1666 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_calc_nrssi_slope_11b()
1942 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_calc_nrssi_slope_11g()
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H A Dif_bwivar.h79 #define CSR_READ_2(sc, reg) \ macro
90 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
95 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
100 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Dbwimac.c176 return CSR_READ_2(sc, data_reg); in bwi_memobj_read_2()
190 ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN); in bwi_memobj_read_4()
195 ret |= CSR_READ_2(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
737 if (CSR_READ_2(sc, 0x50e) & 0x80) in bwi_mac_dummy_xmit()
742 if (CSR_READ_2(sc, 0x50e) & 0x400) in bwi_mac_dummy_xmit()
747 if ((CSR_READ_2(sc, 0x690) & 0x100) == 0) in bwi_mac_dummy_xmit()
1949 CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */ in bwi_mac_unlock()
/freebsd-12.1/sys/dev/vr/
H A Dif_vrreg.h757 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) macro
763 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
764 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-12.1/sys/dev/rl/
H A Dif_rl.c431 return (CSR_READ_2(sc, rl8139_reg)); in rl_miibus_readreg()
1135 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; in rl_rxeof()
1138 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; in rl_rxeof()
1327 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { in rl_twister_update()
1343 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1372 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1470 status = CSR_READ_2(sc, RL_ISR); in rl_poll_locked()
1507 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
1528 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
H A Dif_rlreg.h957 #define CSR_READ_2(sc, reg) \ macro
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-12.1/sys/dev/xl/
H A Dif_xl.c393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); in xl_mii_bitbang_read()
535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) in xl_eeprom_wait()
584 word = CSR_READ_2(sc, XL_W0_EE_DATA); in xl_read_eeprom()
754 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_setmode()
888 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | in xl_reset()
2170 status = CSR_READ_2(sc, XL_STATUS); in xl_intr()
2257 status = CSR_READ_2(sc, XL_STATUS); in xl_poll_locked()
2715 CSR_READ_2(sc, XL_W7_BM_PME); in xl_init_locked()
2944 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_ifmedia_sts()
3133 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_watchdog()
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