1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * NETLOGIC_BSD
31 * $FreeBSD$
32 */
33
34 #ifndef __NLM_HAL_CPUCONTROL_H__
35 #define __NLM_HAL_CPUCONTROL_H__
36
37 #define CPU_BLOCKID_IFU 0
38 #define CPU_BLOCKID_ICU 1
39 #define CPU_BLOCKID_IEU 2
40 #define CPU_BLOCKID_LSU 3
41 #define CPU_BLOCKID_MMU 4
42 #define CPU_BLOCKID_PRF 5
43 #define CPU_BLOCKID_SCH 7
44 #define CPU_BLOCKID_SCU 8
45 #define CPU_BLOCKID_FPU 9
46 #define CPU_BLOCKID_MAP 10
47
48 #define LSU_DEFEATURE 0x304
49 #define LSU_DEBUG_ADDR 0x305
50 #define LSU_DEBUG_DATA0 0x306
51 #define LSU_CERRLOG_REGID 0x09
52 #define SCHED_DEFEATURE 0x700
53
54 /* Offsets of interest from the 'MAP' Block */
55 #define MAP_THREADMODE 0x00
56 #define MAP_EXT_EBASE_ENABLE 0x04
57 #define MAP_CCDI_CONFIG 0x08
58 #define MAP_THRD0_CCDI_STATUS 0x0c
59 #define MAP_THRD1_CCDI_STATUS 0x10
60 #define MAP_THRD2_CCDI_STATUS 0x14
61 #define MAP_THRD3_CCDI_STATUS 0x18
62 #define MAP_THRD0_DEBUG_MODE 0x1c
63 #define MAP_THRD1_DEBUG_MODE 0x20
64 #define MAP_THRD2_DEBUG_MODE 0x24
65 #define MAP_THRD3_DEBUG_MODE 0x28
66 #define MAP_MISC_STATE 0x60
67 #define MAP_DEBUG_READ_CTL 0x64
68 #define MAP_DEBUG_READ_REG0 0x68
69 #define MAP_DEBUG_READ_REG1 0x6c
70
71 #define MMU_SETUP 0x400
72 #define MMU_LFSRSEED 0x401
73 #define MMU_HPW_NUM_PAGE_LVL 0x410
74 #define MMU_PGWKR_PGDBASE 0x411
75 #define MMU_PGWKR_PGDSHFT 0x412
76 #define MMU_PGWKR_PGDMASK 0x413
77 #define MMU_PGWKR_PUDSHFT 0x414
78 #define MMU_PGWKR_PUDMASK 0x415
79 #define MMU_PGWKR_PMDSHFT 0x416
80 #define MMU_PGWKR_PMDMASK 0x417
81 #define MMU_PGWKR_PTESHFT 0x418
82 #define MMU_PGWKR_PTEMASK 0x419
83
84
85 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
86 #if defined(__mips_n64) || defined(__mips_n32)
87 static __inline uint64_t
nlm_mfcr(uint32_t reg)88 nlm_mfcr(uint32_t reg)
89 {
90 uint64_t res;
91
92 __asm__ __volatile__(
93 ".set push\n\t"
94 ".set noreorder\n\t"
95 "move $9, %1\n\t"
96 ".word 0x71280018\n\t" /* mfcr $8, $9 */
97 "move %0, $8\n\t"
98 ".set pop\n"
99 : "=r" (res) : "r"(reg)
100 : "$8", "$9"
101 );
102 return (res);
103 }
104
105 static __inline void
nlm_mtcr(uint32_t reg,uint64_t value)106 nlm_mtcr(uint32_t reg, uint64_t value)
107 {
108 __asm__ __volatile__(
109 ".set push\n\t"
110 ".set noreorder\n\t"
111 "move $8, %0\n"
112 "move $9, %1\n"
113 ".word 0x71280019\n" /* mtcr $8, $9 */
114 ".set pop\n"
115 :
116 : "r" (value), "r" (reg)
117 : "$8", "$9"
118 );
119 }
120
121 #else /* !(defined(__mips_n64) || defined(__mips_n32)) */
122
123 static __inline__ uint64_t
nlm_mfcr(uint32_t reg)124 nlm_mfcr(uint32_t reg)
125 {
126 uint32_t hi, lo;
127
128 __asm__ __volatile__ (
129 ".set push\n"
130 ".set mips64\n"
131 "move $8, %2\n"
132 ".word 0x71090018\n"
133 "nop \n"
134 "dsra32 %0, $9, 0\n"
135 "sll %1, $9, 0\n"
136 ".set pop\n"
137 : "=r"(hi), "=r"(lo)
138 : "r"(reg) : "$8", "$9");
139
140 return (((uint64_t)hi) << 32) | lo;
141 }
142
143 static __inline__ void
nlm_mtcr(uint32_t reg,uint64_t val)144 nlm_mtcr(uint32_t reg, uint64_t val)
145 {
146 uint32_t hi, lo;
147
148 hi = val >> 32;
149 lo = val & 0xffffffff;
150
151 __asm__ __volatile__ (
152 ".set push\n"
153 ".set mips64\n"
154 "move $9, %0\n"
155 "dsll32 $9, %1, 0\n"
156 "dsll32 $8, %0, 0\n"
157 "dsrl32 $9, $9, 0\n"
158 "or $9, $9, $8\n"
159 "move $8, %2\n"
160 ".word 0x71090019\n"
161 "nop \n"
162 ".set pop\n"
163 : :"r"(hi), "r"(lo), "r"(reg)
164 : "$8", "$9");
165 }
166 #endif /* (defined(__mips_n64) || defined(__mips_n32)) */
167
168 /* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
169 * global_mode = 1 to enable global mode, global_mode=0 to disable
170 * clk_gating = 0 to enable clock gating, clk_gating=1 to disable
171 */
nlm_mmu_setup(int hashindex_en,int global_mode,int clk_gating)172 static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
173 int clk_gating)
174 {
175 uint32_t mmusetup = 0;
176
177 mmusetup |= (hashindex_en << 13);
178 mmusetup |= (clk_gating << 3);
179 mmusetup |= (global_mode << 0);
180 nlm_mtcr(MMU_SETUP, mmusetup);
181 }
182
nlm_mmu_lfsr_seed(int thr0_seed,int thr1_seed,int thr2_seed,int thr3_seed)183 static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
184 int thr2_seed, int thr3_seed)
185 {
186 uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
187
188 seed |= ((thr3_seed & 0x7f) << 23);
189 seed |= ((thr2_seed & 0x7f) << 16);
190 seed |= ((thr1_seed & 0x7f) << 7);
191 seed |= ((thr0_seed & 0x7f) << 0);
192 nlm_mtcr(MMU_LFSRSEED, seed);
193 }
194
195 #endif /* __ASSEMBLY__ */
196 #endif /* __NLM_CPUCONTROL_H__ */
197