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Searched refs:BaseR (Results 1 – 5 of 5) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp57 unsigned genElemLoad(MachineInstr *ExtI, unsigned BaseR,
67 unsigned HexagonVExtract::genElemLoad(MachineInstr *ExtI, unsigned BaseR, in genElemLoad() argument
84 .addReg(BaseR) in genElemLoad()
95 .addReg(BaseR) in genElemLoad()
148 unsigned BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in runOnMachineFunction() local
149 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::PS_fi), BaseR) in runOnMachineFunction()
153 unsigned ElemR = genElemLoad(ExtI, BaseR, MRI); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
H A DStore.cpp349 if (const auto *BaseR = dyn_cast<CXXBaseObjectRegion>(MR)) { in attemptDownCast() local
351 MR = BaseR->getSuperRegion(); in attemptDownCast()
438 const SubRegion* BaseR = nullptr; in getLValueFieldOrIvar() local
442 BaseR = cast<SubRegion>(BaseL.castAs<loc::MemRegionVal>().getRegion()); in getLValueFieldOrIvar()
469 return loc::MemRegionVal(MRMgr.getObjCIvarRegion(ID, BaseR)); in getLValueFieldOrIvar()
471 return loc::MemRegionVal(MRMgr.getFieldRegion(cast<FieldDecl>(D), BaseR)); in getLValueFieldOrIvar()
H A DRegionStore.cpp732 const MemRegion *BaseR = E; in RunWorkList() local
734 static_cast<DERIVED*>(this)->VisitCluster(BaseR, getCluster(BaseR)); in RunWorkList()
741 void VisitCluster(const MemRegion *BaseR, const ClusterBindings *C, in VisitCluster() argument
743 static_cast<DERIVED*>(this)->VisitCluster(BaseR, C); in VisitCluster()
991 const MemRegion *BaseR = doNotInvalidateSuperRegion ? R : R->getBaseRegion(); in AddToWorkList() local
992 return AddToWorkList(WorkListElement(BaseR), getCluster(BaseR)); in AddToWorkList()
2426 const MemRegion *BaseR = R->getBaseRegion(); in AddToWorkList() local
2427 return AddToWorkList(WorkListElement(BaseR), getCluster(BaseR)); in AddToWorkList()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp498 unsigned int BaseR = Base.getReg(); in processInstrForSlow3OpLEA() local
503 bool IsInefficientBase = isInefficientLEAReg(BaseR); in processInstrForSlow3OpLEA()
508 if (IsInefficientBase && SSDstR == BaseR && !IsScale1) in processInstrForSlow3OpLEA()
525 if (IsScale1 && (DstR == BaseR || DstR == IndexR)) { in processInstrForSlow3OpLEA()
526 const MachineOperand &Src = DstR == BaseR ? Index : Base; in processInstrForSlow3OpLEA()
558 assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!"); in processInstrForSlow3OpLEA()
563 bool BIK = Base.isKill() && BaseR != IndexR; in processInstrForSlow3OpLEA()
564 TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK); in processInstrForSlow3OpLEA()
/freebsd-12.1/contrib/llvm/lib/Transforms/Utils/
H A DSimplifyLibCalls.cpp1276 APFloat BaseR = APFloat(1.0); in replacePowWithExp() local
1277 BaseR.convert(BaseF->getSemantics(), APFloat::rmTowardZero, &Ignored); in replacePowWithExp()
1278 BaseR = BaseR / *BaseF; in replacePowWithExp()
1280 IsReciprocal = BaseR.isInteger(); in replacePowWithExp()
1281 const APFloat *NF = IsReciprocal ? &BaseR : BaseF; in replacePowWithExp()