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Searched refs:BaseIndex (Results 1 – 12 of 12) sorted by relevance

/freebsd-12.1/contrib/binutils/opcodes/
H A Di386-tbl.h4453 { "bx", Reg16|BaseIndex, 0, 3 },
4455 { "bp", Reg16|BaseIndex, 0, 5 },
4456 { "si", Reg16|BaseIndex, 0, 6 },
4457 { "di", Reg16|BaseIndex, 0, 7 },
4467 { "ecx", Reg32|BaseIndex, 0, 1 },
4468 { "edx", Reg32|BaseIndex, 0, 2 },
4469 { "ebx", Reg32|BaseIndex, 0, 3 },
4471 { "ebp", Reg32|BaseIndex, 0, 5 },
4472 { "esi", Reg32|BaseIndex, 0, 6 },
4473 { "edi", Reg32|BaseIndex, 0, 7 },
[all …]
H A Di386-reg.tbl34 bx, Reg16|BaseIndex, 0, 3
36 bp, Reg16|BaseIndex, 0, 5
37 si, Reg16|BaseIndex, 0, 6
38 di, Reg16|BaseIndex, 0, 7
49 ecx, Reg32|BaseIndex, 0, 1
50 edx, Reg32|BaseIndex, 0, 2
51 ebx, Reg32|BaseIndex, 0, 3
53 ebp, Reg32|BaseIndex, 0, 5
54 esi, Reg32|BaseIndex, 0, 6
55 edi, Reg32|BaseIndex, 0, 7
[all …]
H A Di386-opc.tbl413 … 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Base…
415 … 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Base…
421 lods, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
422 lods, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc }
424 slod, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
425 slod, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc }
427 …vs, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseInd…
429 …ov, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseInd…
431 scas, 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
1193 …No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseInd…
[all …]
H A Di386-opc.h159 #define BaseIndex 0x800 macro
200 #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DVirtRegMap.cpp360 SlotIndex BaseIndex = LIS->getInstructionIndex(MI); in readsUndefSubreg() local
363 assert(LI.liveAt(BaseIndex) && in readsUndefSubreg()
370 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex)) in readsUndefSubreg()
H A DCodeGenPrepare.cpp5194 Value *BaseIndex = ConstantInt::get(IntPtrTy, BaseOffset); in splitLargeGEPOffsets() local
5199 NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep"); in splitLargeGEPOffsets()
/freebsd-12.1/contrib/binutils/gas/config/
H A Dtc-i386.c1452 { BaseIndex, "BaseIndex" },
2471 if (!disp && (i.types[op] & BaseIndex)) in optimize_disp()
4956 && (i.base_reg->reg_type != BaseIndex in i386_index_check()
4960 != (RegXX | BaseIndex)))) in i386_index_check()
4970 != (Reg16 | BaseIndex))) in i386_index_check()
4973 != (Reg16 | BaseIndex)) in i386_index_check()
4987 != (Reg32 | BaseIndex)))) in i386_index_check()
5188 i.types[this_operand] |= BaseIndex; in i386_operand()
7387 i.types[this_operand] |= BaseIndex; in intel_e11()
7429 i.types[this_operand] |= BaseIndex; in intel_e11()
[all …]
/freebsd-12.1/contrib/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp351 unsigned BaseIndex = 0) { in getSameOpcode() argument
354 return InstructionsState(VL[BaseIndex], nullptr, nullptr); in getSameOpcode()
356 bool IsCastOp = isa<CastInst>(VL[BaseIndex]); in getSameOpcode()
357 bool IsBinOp = isa<BinaryOperator>(VL[BaseIndex]); in getSameOpcode()
358 unsigned Opcode = cast<Instruction>(VL[BaseIndex])->getOpcode(); in getSameOpcode()
360 unsigned AltIndex = BaseIndex; in getSameOpcode()
375 Type *Ty0 = cast<Instruction>(VL[BaseIndex])->getOperand(0)->getType(); in getSameOpcode()
388 return InstructionsState(VL[BaseIndex], nullptr, nullptr); in getSameOpcode()
391 return InstructionsState(VL[BaseIndex], cast<Instruction>(VL[BaseIndex]), in getSameOpcode()
/freebsd-12.1/contrib/llvm/lib/IR/
H A DVerifier.cpp4414 const int BaseIndex = cast<ConstantInt>(Base)->getZExtValue(); in visitIntrinsicCall() local
4417 Assert(0 <= BaseIndex && BaseIndex < (int)StatepointCall.arg_size(), in visitIntrinsicCall()
4447 Assert(GCParamArgsStart <= BaseIndex && BaseIndex < GCParamArgsEnd, in visitIntrinsicCall()
/freebsd-12.1/contrib/binutils/include/opcode/
H A DChangeLog-91031533 (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
1538 * i386.h (i386_regtab): Remove BaseIndex modifier from esp.
1560 (i386_regtab): Add BaseIndex to 32 bit regs reg_type.
/freebsd-12.1/contrib/llvm/tools/clang/lib/AST/
H A DExprConstant.cpp1976 unsigned BaseIndex = 0; in CheckConstantExpression() local
1979 Value.getStructBase(BaseIndex), Usage)) in CheckConstantExpression()
1981 ++BaseIndex; in CheckConstantExpression()
/freebsd-12.1/contrib/binutils/gas/
H A DChangeLog-00013750 (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,