| /freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 30 ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const { in lowerCall() argument
40 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, in lowerCall()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 522 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
525 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
526 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCallArguments()
533 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments()
537 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { in LowerCallArguments()
540 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 213 unsigned ResReg, ArrayRef<unsigned> ArgRegs,
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 223 SmallVectorImpl<unsigned> &ArgRegs,
1897 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument
1964 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2235 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local
2239 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2255 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2263 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2344 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local
2349 ArgRegs.reserve(arg_size); in SelectCall()
2389 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 182 SmallVectorImpl<unsigned> &ArgRegs,
1376 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1433 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1607 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1612 ArgRegs.reserve(NumArgs); in fastLowerCall()
1638 ArgRegs.push_back(Arg); in fastLowerCall()
1647 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| H A D | PPCISelLowering.cpp | 3170 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
3174 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
3176 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
3183 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
3198 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
3202 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3204 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3211 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3223 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
3228 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1165 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); in LowerFormalArguments() local
1166 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
1179 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
1183 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
1203 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
1206 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1339 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1343 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1344 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1348 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1358 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4162 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4173 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4222 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4246 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
4247 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
4258 if (ArgRegs.size() == Idx) in writeVarArgRegs()
4263 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4275 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
4277 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 135 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
139 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd()
140 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd()
144 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 536 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3261 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
3306 ArgRegs.push_back(ResultReg); in fastLowerCall()
3338 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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