Searched refs:AddSubOpc (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
357 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
360 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| H A D | ARMBaseInstrInfo.h | 424 unsigned &AddSubOpc, bool &NegAcc,
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| H A D | ARMBaseInstrInfo.cpp | 82 uint16_t AddSubOpc; // Expanded add / sub opcode member
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4569 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4577 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 8942 unsigned ShiftAmt, AddSubOpc; in performMulCombine() local
8956 AddSubOpc = ISD::ADD; in performMulCombine()
8959 AddSubOpc = ISD::SUB; in performMulCombine()
8969 AddSubOpc = ISD::SUB; in performMulCombine()
8973 AddSubOpc = ISD::ADD; in performMulCombine()
8986 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
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