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Searched refs:wr32 (Results 1 – 25 of 27) sorted by relevance

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/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb_hw.c35 wr32(hw, TXGBE_ARBRXCTL, reg); in txgbe_dcb_config_rx_arbiter_raptor()
47 wr32(hw, TXGBE_RPUP2TC, reg); in txgbe_dcb_config_rx_arbiter_raptor()
68 wr32(hw, TXGBE_ARBRXCTL, reg); in txgbe_dcb_config_rx_arbiter_raptor()
91 wr32(hw, TXGBE_QARBTXCRED(i), 0); in txgbe_dcb_config_tx_desc_arbiter_raptor()
114 wr32(hw, TXGBE_ARBTXCTL, reg); in txgbe_dcb_config_tx_desc_arbiter_raptor()
144 wr32(hw, TXGBE_PARBTXCTL, reg); in txgbe_dcb_config_tx_data_arbiter_raptor()
156 wr32(hw, TXGBE_PBRXUP2TC, reg); in txgbe_dcb_config_tx_data_arbiter_raptor()
178 wr32(hw, TXGBE_PARBTXCTL, reg); in txgbe_dcb_config_tx_data_arbiter_raptor()
234 wr32(hw, TXGBE_FCWTRLO(i), 0); in txgbe_dcb_config_pfc_raptor()
241 wr32(hw, TXGBE_FCWTRLO(i), 0); in txgbe_dcb_config_pfc_raptor()
[all …]
H A Dtxgbe_hw.c298 wr32(hw, TXGBE_ARBPOOLIDX, i); in txgbe_start_hw_gen2()
299 wr32(hw, TXGBE_ARBTXRATE, 0); in txgbe_start_hw_gen2()
472 wr32(hw, TXGBE_ETHADDRIDX, 0); in txgbe_get_mac_addr()
536 wr32(hw, TXGBE_IENMISC, 0); in txgbe_stop_hw()
720 wr32(hw, TXGBE_ETHADDRL, 0); in txgbe_clear_rar()
783 wr32(hw, TXGBE_ETHADDRL, 0); in txgbe_init_rx_addrs()
784 wr32(hw, TXGBE_ETHADDRH, 0); in txgbe_init_rx_addrs()
1840 wr32(hw, TXGBE_PSRVLAN, 0); in txgbe_set_vlvf()
1887 wr32(hw, TXGBE_PSRVLAN, 0); in txgbe_clear_vfta()
2276 wr32(hw, TXGBE_TSINTR, in txgbe_init_thermal_sensor_thresh()
[all …]
H A Dtxgbe_dcb.c115 wr32(hw, TXGBE_RXFCCFG, mflcn_reg); in txgbe_dcb_pfc_enable()
116 wr32(hw, TXGBE_TXFCCFG, fccfg_reg); in txgbe_dcb_pfc_enable()
135 wr32(hw, TXGBE_FCWTRLO(tc_num), fcrtl); in txgbe_dcb_pfc_enable()
136 wr32(hw, TXGBE_FCWTRHI(tc_num), fcrth); in txgbe_dcb_pfc_enable()
141 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001); in txgbe_dcb_pfc_enable()
144 wr32(hw, TXGBE_RXFCRFSH, pause_time / 2); in txgbe_dcb_pfc_enable()
H A Dtxgbe_mbx.c128 wr32(hw, TXGBE_MBVFICR(index), mask); in txgbe_check_for_bit_pf()
201 wr32(hw, TXGBE_FLRVFEC(reg_offset), (1 << vf_shift)); in txgbe_check_for_rst_pf()
223 wr32(hw, TXGBE_MBCTL(vf_number), TXGBE_MBCTL_PFU); in txgbe_obtain_mbx_lock_pf()
266 wr32(hw, TXGBE_MBCTL(vf_number), TXGBE_MBCTL_STS); in txgbe_write_mbx_pf()
303 wr32(hw, TXGBE_MBCTL(vf_number), TXGBE_MBCTL_ACK); in txgbe_read_mbx_pf()
H A Dtxgbe_phy.c320 wr32(hw, TXGBE_MDIOSCA, command); in txgbe_read_phy_reg_mdi()
324 wr32(hw, TXGBE_MDIOSCD, command); in txgbe_read_phy_reg_mdi()
386 wr32(hw, TXGBE_MDIOSCA, command); in txgbe_write_phy_reg_mdi()
391 wr32(hw, TXGBE_MDIOSCD, command); in txgbe_write_phy_reg_mdi()
1239 wr32(hw, TXGBE_I2CDATA, in txgbe_read_i2c_byte_unlocked()
1351 wr32(hw, TXGBE_I2CENA, 0); in txgbe_i2c_start()
1353 wr32(hw, TXGBE_I2CCON, in txgbe_i2c_start()
1362 wr32(hw, TXGBE_I2CTXTL, 4); in txgbe_i2c_start()
1366 wr32(hw, TXGBE_I2CICM, 0); in txgbe_i2c_start()
1367 wr32(hw, TXGBE_I2CENA, 1); in txgbe_i2c_start()
[all …]
H A Dtxgbe_regs.h1787 wr32(hw, reg, val); in wr32m()
1801 wr32(hw, reg, (u32)val); in wr64()
1802 wr32(hw, reg + 4, (u32)(val >> 32)); in wr64()
1839 wr32((hw), (reg) + ((idx) << 2), (val))
1847 wr32((hw), reg, val); \
1859 wr32(hw, TXGBE_XPCS_IDAADDR, addr); in rd32_epcs()
1867 wr32(hw, TXGBE_XPCS_IDAADDR, addr); in wr32_epcs()
1868 wr32(hw, TXGBE_XPCS_IDADATA, data); in wr32_epcs()
1875 wr32(hw, TXGBE_EPHY_IDAADDR, addr); in rd32_ephy()
1883 wr32(hw, TXGBE_EPHY_IDAADDR, addr); in wr32_ephy()
[all …]
/f-stack/dpdk/drivers/net/txgbe/
H A Dtxgbe_pf.c195 wr32(hw, TXGBE_ETFLT(i), in txgbe_add_tx_flow_control_drop_filter()
227 wr32(hw, TXGBE_POOLCTL, vtctl); in txgbe_pf_host_configure()
245 wr32(hw, TXGBE_ETHADDRASSL, 0); in txgbe_pf_host_configure()
246 wr32(hw, TXGBE_ETHADDRASSH, 0); in txgbe_pf_host_configure()
271 wr32(hw, TXGBE_PORTCTL, gcr_ext); in txgbe_pf_host_configure()
272 wr32(hw, TXGBE_GPIE, gpie); in txgbe_pf_host_configure()
279 wr32(hw, TXGBE_VLANCTL, vlanctrl); in txgbe_pf_host_configure()
290 wr32(hw, TXGBE_FCWTRLO(i), 0); in txgbe_pf_host_configure()
292 wr32(hw, TXGBE_FCWTRHI(i), fcrth); in txgbe_pf_host_configure()
341 wr32(hw, TXGBE_PSRCTL, fctrl); in txgbe_set_rx_mode()
[all …]
H A Dtxgbe_rxtx.c2832 wr32(hw, TXGBE_RACTL, mrqc); in txgbe_dev_rss_hash_update()
3009 wr32(hw, TXGBE_POOLRXENA(0), in txgbe_vmdq_dcb_configure()
3012 wr32(hw, TXGBE_ETHADDRIDX, 0); in txgbe_vmdq_dcb_configure()
3044 wr32(hw, TXGBE_ARBTXCTL, reg); in txgbe_dcb_tx_hw_config()
3055 wr32(hw, TXGBE_PORTCTL, reg); in txgbe_dcb_tx_hw_config()
3060 wr32(hw, TXGBE_ARBTXCTL, reg); in txgbe_dcb_tx_hw_config()
3078 wr32(hw, TXGBE_POOLTXENA(0), in txgbe_vmdq_dcb_hw_tx_config()
3236 wr32(hw, TXGBE_POOLCTL, 0); in txgbe_dcb_rx_hw_config()
3244 wr32(hw, TXGBE_POOLCTL, 0); in txgbe_dcb_rx_hw_config()
3247 wr32(hw, TXGBE_PORTCTL, reg); in txgbe_dcb_rx_hw_config()
[all …]
H A Dtxgbe_ethdev.c981 wr32(hw, TXGBE_PORTCTL, ctrl); in txgbe_vlan_hw_extend_disable()
999 wr32(hw, TXGBE_PORTCTL, ctrl); in txgbe_vlan_hw_extend_enable()
2509 wr32(hw, TXGBE_PSRCTL, fctrl); in txgbe_dev_promiscuous_enable()
2526 wr32(hw, TXGBE_PSRCTL, fctrl); in txgbe_dev_promiscuous_disable()
2539 wr32(hw, TXGBE_PSRCTL, fctrl); in txgbe_dev_allmulticast_enable()
2555 wr32(hw, TXGBE_PSRCTL, fctrl); in txgbe_dev_allmulticast_disable()
3331 wr32(hw, TXGBE_IMS(0), mask); in txgbe_dev_rx_queue_intr_enable()
3430 wr32(hw, TXGBE_GPIE, gpie); in txgbe_configure_msix()
3644 wr32(hw, TXGBE_TSTIMEL, 0x0); in txgbe_timesync_enable()
3645 wr32(hw, TXGBE_TSTIMEH, 0x0); in txgbe_timesync_enable()
[all …]
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_hmc.h110 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
111 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
112 wr32((hw), I40E_PFHMC_SDCMD, val3); \
129 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
130 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
131 wr32((hw), I40E_PFHMC_SDCMD, val3); \
141 wr32((hw), I40E_PFHMC_PDINV, \
H A Di40e_adminq.c277 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
278 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
324 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
325 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
502 wr32(hw, hw->aq.asq.head, 0); in i40e_shutdown_asq()
504 wr32(hw, hw->aq.asq.len, 0); in i40e_shutdown_asq()
505 wr32(hw, hw->aq.asq.bal, 0); in i40e_shutdown_asq()
506 wr32(hw, hw->aq.asq.bah, 0); in i40e_shutdown_asq()
538 wr32(hw, hw->aq.arq.len, 0); in i40e_shutdown_arq()
539 wr32(hw, hw->aq.arq.bal, 0); in i40e_shutdown_arq()
[all …]
H A Di40e_diag.c42 wr32(hw, reg, (pat & mask)); in i40e_diag_reg_pattern_test()
49 wr32(hw, reg, orig_val); in i40e_diag_reg_pattern_test()
H A Di40e_lan_hmc.c492 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
494 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
498 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
500 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
504 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id), in i40e_configure_lan_hmc()
506 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
510 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id), in i40e_configure_lan_hmc()
512 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
H A Di40e_common.c1406 wr32(hw, I40E_PFGEN_CTRL, in i40e_pf_reset()
1478 wr32(hw, I40E_PFINT_ICR0_ENA, 0); in i40e_clear_hw()
1485 wr32(hw, I40E_PFINT_LNKLST0, val); in i40e_clear_hw()
1487 wr32(hw, I40E_PFINT_LNKLSTN(i), val); in i40e_clear_hw()
1490 wr32(hw, I40E_VPINT_LNKLST0(i), val); in i40e_clear_hw()
1515 wr32(hw, I40E_QINT_TQCTL(i), 0); in i40e_clear_hw()
1516 wr32(hw, I40E_QTX_ENA(i), 0); in i40e_clear_hw()
1517 wr32(hw, I40E_QINT_RQCTL(i), 0); in i40e_clear_hw()
1518 wr32(hw, I40E_QRX_ENA(i), 0); in i40e_clear_hw()
1968 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); in i40e_aq_clear_pxe_mode()
[all …]
H A Di40e_osdep.h154 #define wr32(a, reg, value) \ macro
/f-stack/dpdk/drivers/common/iavf/
H A Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
451 wr32(hw, hw->aq.asq.head, 0); in iavf_shutdown_asq()
453 wr32(hw, hw->aq.asq.len, 0); in iavf_shutdown_asq()
454 wr32(hw, hw->aq.asq.bal, 0); in iavf_shutdown_asq()
455 wr32(hw, hw->aq.asq.bah, 0); in iavf_shutdown_asq()
487 wr32(hw, hw->aq.arq.len, 0); in iavf_shutdown_arq()
488 wr32(hw, hw->aq.arq.bal, 0); in iavf_shutdown_arq()
[all …]
H A Diavf_osdep.h110 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) macro
127 #define IAVF_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_controlq.c236 wr32(hw, ring->head, 0); in ice_cfg_cq_regs()
237 wr32(hw, ring->tail, 0); in ice_cfg_cq_regs()
450 wr32(hw, cq->sq.head, 0); in ice_shutdown_sq()
451 wr32(hw, cq->sq.tail, 0); in ice_shutdown_sq()
452 wr32(hw, cq->sq.len, 0); in ice_shutdown_sq()
453 wr32(hw, cq->sq.bal, 0); in ice_shutdown_sq()
454 wr32(hw, cq->sq.bah, 0); in ice_shutdown_sq()
515 wr32(hw, cq->rq.head, 0); in ice_shutdown_rq()
517 wr32(hw, cq->rq.len, 0); in ice_shutdown_rq()
518 wr32(hw, cq->rq.bal, 0); in ice_shutdown_rq()
[all …]
H A Dice_osdep.h118 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) macro
171 #define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
H A Dice_common.c736 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); in ice_init_hw()
961 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); in ice_pf_reset()
1016 wr32(hw, GLGEN_RTRIG, val); in ice_reset()
1044 wr32(hw, QRX_CONTEXT(i, rxq_index), in ice_copy_rxq_ctx_to_hw()
1121 wr32(hw, QRX_CONTEXT(i, rxq_index), 0); in ice_clear_rxq_ctx()
1182 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), in ice_copy_tx_cmpltnq_ctx_to_hw()
1245 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); in ice_clear_tx_cmpltnq_ctx()
1272 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), in ice_copy_tx_drbell_q_ctx_to_hw()
1337 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); in ice_clear_tx_drbell_q_ctx()
4556 wr32(hw, GLV_REPC(vsi_num), 0); in ice_stat_update_repc()
[all …]
H A Dice_flex_pipe.c1268 wr32(hw, GL_PREEXT_L2_PMASK0(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_L); in ice_init_pkg_regs()
1269 wr32(hw, GL_PREEXT_L2_PMASK1(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_H); in ice_init_pkg_regs()
3076 wr32(hw, offset, val); in ice_write_prof_mask_reg()
3107 wr32(hw, offset, enable_mask); in ice_write_prof_mask_enable_res()
4387 wr32(hw, GLQF_FDMASK_SEL(prof_id), mask_sel); in ice_update_fd_mask()
4564 wr32(hw, GLQF_FDSWAP(prof_id, j), raw_swap); in ice_update_fd_swap()
4570 wr32(hw, GLQF_FDINSET(prof_id, j), raw_in); in ice_update_fd_swap()
H A Dice_nvm.c1128 wr32(hw, cmd->offset, data->regval); in ice_nvm_access_write()
/f-stack/freebsd/mips/malta/
H A Dgt_pci_bus_space.c223 #define wr32(a, v) writel(a, htole32(v)) macro
310 wr32(bsh + offset, value); in gt_pci_bs_w_4()
334 wr32(baddr, *addr++); in gt_pci_bs_wm_4()
360 wr32(baddr, *addr++); in gt_pci_bs_wr_4()
386 wr32(addr, value); in gt_pci_bs_sm_4()
410 wr32(addr, value); in gt_pci_bs_sr_4()
/f-stack/freebsd/mips/cavium/
H A Doctopci_bus_space.c204 #define wr32(a, v) cvmx_write64_uint32(a, htole32(v)) macro
356 wr32(bsh + offset, value); in octopci_bs_w_4()
390 wr32(baddr, *addr++); in octopci_bs_wm_4()
428 wr32(baddr, *addr++); in octopci_bs_wr_4()
464 wr32(addr, value); in octopci_bs_sm_4()
498 wr32(addr, value); in octopci_bs_sr_4()
556 wr32(addr2, rd32(addr1)); in octopci_bs_c_4()
561 wr32(addr2, rd32(addr1)); in octopci_bs_c_4()
/f-stack/freebsd/mips/mips/
H A Dbus_space_generic.c203 #define wr32(a, v) cvmx_write64_uint32(a, v) macro
214 #define wr32(a, v) writel(a, v) macro
428 wr32(bsh + offset, value); in generic_bs_w_4()
474 wr32(baddr, *addr++); in generic_bs_wm_4()
526 wr32(baddr, *addr++); in generic_bs_wr_4()
578 wr32(addr, value); in generic_bs_sm_4()
626 wr32(addr, value); in generic_bs_sr_4()
698 wr32(addr2, rd32(addr1)); in generic_bs_c_4()
703 wr32(addr2, rd32(addr1)); in generic_bs_c_4()

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