1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
3 */
4
5 #ifndef _ICE_TYPE_H_
6 #define _ICE_TYPE_H_
7
8 #define ETH_ALEN 6
9
10 #define ETH_HEADER_LEN 14
11
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
14
15 #define BITS_PER_BYTE 8
16
17 #define _FORCE_
18
19 #define ICE_BYTES_PER_WORD 2
20 #define ICE_BYTES_PER_DWORD 4
21 #define ICE_MAX_TRAFFIC_CLASS 8
22
23 /**
24 * ROUND_UP - round up to next arbitrary multiple (not a power of 2)
25 * @a: value to round up
26 * @b: arbitrary multiple
27 *
28 * Round up to the next multiple of the arbitrary b.
29 * Note, when b is a power of 2 use ICE_ALIGN() instead.
30 */
31 #define ROUND_UP(a, b) ((b) * DIVIDE_AND_ROUND_UP((a), (b)))
32
33 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
34
35 #define IS_ASCII(_ch) ((_ch) < 0x80)
36
37 #define STRUCT_HACK_VAR_LEN
38 /**
39 * ice_struct_size - size of struct with C99 flexible array member
40 * @ptr: pointer to structure
41 * @field: flexible array member (last member of the structure)
42 * @num: number of elements of that flexible array member
43 */
44 #define ice_struct_size(ptr, field, num) \
45 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
46
47 #ifndef FLEX_ARRAY_SIZE
48 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
49 #endif /* FLEX_ARRAY_SIZE */
50
51 #include "ice_status.h"
52 #include "ice_hw_autogen.h"
53 #include "ice_devids.h"
54 #include "ice_osdep.h"
55 #include "ice_bitops.h" /* Must come before ice_controlq.h */
56 #include "ice_controlq.h"
57 #include "ice_lan_tx_rx.h"
58 #include "ice_flex_type.h"
59 #include "ice_protocol_type.h"
60
61 /**
62 * ice_is_pow2 - check if integer value is a power of 2
63 * @val: unsigned integer to be validated
64 */
ice_is_pow2(u64 val)65 static inline bool ice_is_pow2(u64 val)
66 {
67 return (val && !(val & (val - 1)));
68 }
69
70 /**
71 * ice_ilog2 - Calculates integer log base 2 of a number
72 * @n: number on which to perform operation
73 */
ice_ilog2(u64 n)74 static inline int ice_ilog2(u64 n)
75 {
76 int i;
77
78 for (i = 63; i >= 0; i--)
79 if (((u64)1 << i) & n)
80 return i;
81
82 return -1;
83 }
84
ice_is_tc_ena(ice_bitmap_t bitmap,u8 tc)85 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
86 {
87 return ice_is_bit_set(&bitmap, tc);
88 }
89
90 #define DIV_64BIT(n, d) ((n) / (d))
91
round_up_64bit(u64 a,u32 b)92 static inline u64 round_up_64bit(u64 a, u32 b)
93 {
94 return DIV_64BIT(((a) + (b) / 2), (b));
95 }
96
ice_round_to_num(u32 N,u32 R)97 static inline u32 ice_round_to_num(u32 N, u32 R)
98 {
99 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
100 ((((N) + (R) - 1) / (R)) * (R)));
101 }
102
103 /* Driver always calls main vsi_handle first */
104 #define ICE_MAIN_VSI_HANDLE 0
105
106 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
107 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
108
109 /* Data type manipulation macros. */
110 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
111 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
112 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
113 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
114
115 /* debug masks - set these bits in hw->debug_mask to control output */
116 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
117 #define ICE_DBG_INIT BIT_ULL(1)
118 #define ICE_DBG_RELEASE BIT_ULL(2)
119 #define ICE_DBG_FW_LOG BIT_ULL(3)
120 #define ICE_DBG_LINK BIT_ULL(4)
121 #define ICE_DBG_PHY BIT_ULL(5)
122 #define ICE_DBG_QCTX BIT_ULL(6)
123 #define ICE_DBG_NVM BIT_ULL(7)
124 #define ICE_DBG_LAN BIT_ULL(8)
125 #define ICE_DBG_FLOW BIT_ULL(9)
126 #define ICE_DBG_DCB BIT_ULL(10)
127 #define ICE_DBG_DIAG BIT_ULL(11)
128 #define ICE_DBG_FD BIT_ULL(12)
129 #define ICE_DBG_SW BIT_ULL(13)
130 #define ICE_DBG_SCHED BIT_ULL(14)
131
132 #define ICE_DBG_PKG BIT_ULL(16)
133 #define ICE_DBG_RES BIT_ULL(17)
134 #define ICE_DBG_ACL BIT_ULL(18)
135 #define ICE_DBG_AQ_MSG BIT_ULL(24)
136 #define ICE_DBG_AQ_DESC BIT_ULL(25)
137 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
138 #define ICE_DBG_AQ_CMD BIT_ULL(27)
139 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
140 ICE_DBG_AQ_DESC | \
141 ICE_DBG_AQ_DESC_BUF | \
142 ICE_DBG_AQ_CMD)
143
144 #define ICE_DBG_USER BIT_ULL(31)
145 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
146
147 #define __ALWAYS_UNUSED
148
149 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
150 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
151 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
152 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
153
154 enum ice_aq_res_ids {
155 ICE_NVM_RES_ID = 1,
156 ICE_SPD_RES_ID,
157 ICE_CHANGE_LOCK_RES_ID,
158 ICE_GLOBAL_CFG_LOCK_RES_ID
159 };
160
161 /* FW update timeout definitions are in milliseconds */
162 #define ICE_NVM_TIMEOUT 180000
163 #define ICE_CHANGE_LOCK_TIMEOUT 1000
164 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
165
166 enum ice_aq_res_access_type {
167 ICE_RES_READ = 1,
168 ICE_RES_WRITE
169 };
170
171 struct ice_driver_ver {
172 u8 major_ver;
173 u8 minor_ver;
174 u8 build_ver;
175 u8 subbuild_ver;
176 u8 driver_string[32];
177 };
178
179 enum ice_fc_mode {
180 ICE_FC_NONE = 0,
181 ICE_FC_RX_PAUSE,
182 ICE_FC_TX_PAUSE,
183 ICE_FC_FULL,
184 ICE_FC_AUTO,
185 ICE_FC_PFC,
186 ICE_FC_DFLT
187 };
188
189 enum ice_phy_cache_mode {
190 ICE_FC_MODE = 0,
191 ICE_SPEED_MODE,
192 ICE_FEC_MODE
193 };
194
195 enum ice_fec_mode {
196 ICE_FEC_NONE = 0,
197 ICE_FEC_RS,
198 ICE_FEC_BASER,
199 ICE_FEC_AUTO
200 };
201
202 struct ice_phy_cache_mode_data {
203 union {
204 enum ice_fec_mode curr_user_fec_req;
205 enum ice_fc_mode curr_user_fc_req;
206 u16 curr_user_speed_req;
207 } data;
208 };
209
210 enum ice_set_fc_aq_failures {
211 ICE_SET_FC_AQ_FAIL_NONE = 0,
212 ICE_SET_FC_AQ_FAIL_GET,
213 ICE_SET_FC_AQ_FAIL_SET,
214 ICE_SET_FC_AQ_FAIL_UPDATE
215 };
216
217 /* These are structs for managing the hardware information and the operations */
218 /* MAC types */
219 enum ice_mac_type {
220 ICE_MAC_UNKNOWN = 0,
221 ICE_MAC_E810,
222 ICE_MAC_GENERIC,
223 };
224
225 /* Media Types */
226 enum ice_media_type {
227 ICE_MEDIA_UNKNOWN = 0,
228 ICE_MEDIA_FIBER,
229 ICE_MEDIA_BASET,
230 ICE_MEDIA_BACKPLANE,
231 ICE_MEDIA_DA,
232 ICE_MEDIA_AUI,
233 };
234
235 /* Software VSI types. */
236 enum ice_vsi_type {
237 ICE_VSI_PF = 0,
238 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
239 ICE_VSI_LB = 6,
240 };
241
242 struct ice_link_status {
243 /* Refer to ice_aq_phy_type for bits definition */
244 u64 phy_type_low;
245 u64 phy_type_high;
246 u8 topo_media_conflict;
247 u16 max_frame_size;
248 u16 link_speed;
249 u16 req_speeds;
250 u8 lse_ena; /* Link Status Event notification */
251 u8 link_info;
252 u8 an_info;
253 u8 ext_info;
254 u8 fec_info;
255 u8 pacing;
256 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
257 * ice_aqc_get_phy_caps structure
258 */
259 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
260 };
261
262 /* Different data queue types: These are mainly for SW consumption. */
263 enum ice_q {
264 ICE_DATA_Q_DOORBELL,
265 ICE_DATA_Q_CMPL,
266 ICE_DATA_Q_QUANTA,
267 ICE_DATA_Q_RX,
268 ICE_DATA_Q_TX,
269 };
270
271 /* Different reset sources for which a disable queue AQ call has to be made in
272 * order to clean the Tx scheduler as a part of the reset
273 */
274 enum ice_disq_rst_src {
275 ICE_NO_RESET = 0,
276 ICE_VM_RESET,
277 };
278
279 /* PHY info such as phy_type, etc... */
280 struct ice_phy_info {
281 struct ice_link_status link_info;
282 struct ice_link_status link_info_old;
283 u64 phy_type_low;
284 u64 phy_type_high;
285 enum ice_media_type media_type;
286 u8 get_link_info;
287 /* Please refer to struct ice_aqc_get_link_status_data to get
288 * detail of enable bit in curr_user_speed_req
289 */
290 u16 curr_user_speed_req;
291 enum ice_fec_mode curr_user_fec_req;
292 enum ice_fc_mode curr_user_fc_req;
293 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
294 };
295
296 #define ICE_MAX_NUM_MIRROR_RULES 64
297
298 /* protocol enumeration for filters */
299 enum ice_fltr_ptype {
300 /* NONE - used for undef/error */
301 ICE_FLTR_PTYPE_NONF_NONE = 0,
302 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
303 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
304 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
305 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
306 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
307 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
308 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
309 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
310 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
311 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_OTHER,
312 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_EH_IPV6_OTHER,
313 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
314 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
315 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
316 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
317 ICE_FLTR_PTYPE_NONF_IPV4_AH,
318 ICE_FLTR_PTYPE_NONF_IPV6_AH,
319 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
320 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
321 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
322 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
323 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
324 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
325 ICE_FLTR_PTYPE_NON_IP_L2,
326 ICE_FLTR_PTYPE_FRAG_IPV4,
327 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
328 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
329 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
330 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
331 ICE_FLTR_PTYPE_MAX,
332 };
333
334 enum ice_fd_hw_seg {
335 ICE_FD_HW_SEG_NON_TUN = 0,
336 ICE_FD_HW_SEG_TUN,
337 ICE_FD_HW_SEG_MAX,
338 };
339
340 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
341 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
342
343 struct ice_fd_hw_prof {
344 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
345 int cnt;
346 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
347 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
348 };
349
350 /* Common HW capabilities for SW use */
351 struct ice_hw_common_caps {
352 /* Write CSR protection */
353 u64 wr_csr_prot;
354 u32 switching_mode;
355 /* switching mode supported - EVB switching (including cloud) */
356 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
357
358 /* Manageablity mode & supported protocols over MCTP */
359 u32 mgmt_mode;
360 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
361 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
362 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
363
364 u32 mgmt_protocols_mctp;
365 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
366 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
367 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
368 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
369
370 u32 os2bmc;
371 u32 valid_functions;
372 /* DCB capabilities */
373 u32 active_tc_bitmap;
374 u32 maxtc;
375
376 /* RSS related capabilities */
377 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
378 u32 rss_table_entry_width; /* RSS Entry width in bits */
379
380 /* Tx/Rx queues */
381 u32 num_rxq; /* Number/Total Rx queues */
382 u32 rxq_first_id; /* First queue ID for Rx queues */
383 u32 num_txq; /* Number/Total Tx queues */
384 u32 txq_first_id; /* First queue ID for Tx queues */
385
386 /* MSI-X vectors */
387 u32 num_msix_vectors;
388 u32 msix_vector_first_id;
389
390 /* Max MTU for function or device */
391 u32 max_mtu;
392
393 /* WOL related */
394 u32 num_wol_proxy_fltr;
395 u32 wol_proxy_vsi_seid;
396
397 /* LED/SDP pin count */
398 u32 led_pin_num;
399 u32 sdp_pin_num;
400
401 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
402 #define ICE_MAX_SUPPORTED_GPIO_LED 12
403 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
404 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
405 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
406
407 /* EVB capabilities */
408 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
409 u8 evb_802_1_qbh; /* Bridge Port Extension */
410
411 u8 dcb;
412 u8 iscsi;
413 u8 mgmt_cem;
414
415 /* WoL and APM support */
416 #define ICE_WOL_SUPPORT_M BIT(0)
417 #define ICE_ACPI_PROG_MTHD_M BIT(1)
418 #define ICE_PROXY_SUPPORT_M BIT(2)
419 u8 apm_wol_support;
420 u8 acpi_prog_mthd;
421 u8 proxy_support;
422 bool nvm_unified_update;
423 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
424 };
425
426 /* Function specific capabilities */
427 struct ice_hw_func_caps {
428 struct ice_hw_common_caps common_cap;
429 u32 guar_num_vsi;
430 u32 fd_fltr_guar; /* Number of filters guaranteed */
431 u32 fd_fltr_best_effort; /* Number of best effort filters */
432 };
433
434 /* Device wide capabilities */
435 struct ice_hw_dev_caps {
436 struct ice_hw_common_caps common_cap;
437 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
438 u32 num_flow_director_fltr; /* Number of FD filters available */
439 u32 num_funcs;
440 };
441
442 /* Information about MAC such as address, etc... */
443 struct ice_mac_info {
444 u8 lan_addr[ETH_ALEN];
445 u8 perm_addr[ETH_ALEN];
446 u8 port_addr[ETH_ALEN];
447 u8 wol_addr[ETH_ALEN];
448 };
449
450 /* PCI bus types */
451 enum ice_bus_type {
452 ice_bus_unknown = 0,
453 ice_bus_pci_express,
454 ice_bus_embedded, /* Is device Embedded versus card */
455 ice_bus_reserved
456 };
457
458 /* PCI bus speeds */
459 enum ice_pcie_bus_speed {
460 ice_pcie_speed_unknown = 0xff,
461 ice_pcie_speed_2_5GT = 0x14,
462 ice_pcie_speed_5_0GT = 0x15,
463 ice_pcie_speed_8_0GT = 0x16,
464 ice_pcie_speed_16_0GT = 0x17
465 };
466
467 /* PCI bus widths */
468 enum ice_pcie_link_width {
469 ice_pcie_lnk_width_resrv = 0x00,
470 ice_pcie_lnk_x1 = 0x01,
471 ice_pcie_lnk_x2 = 0x02,
472 ice_pcie_lnk_x4 = 0x04,
473 ice_pcie_lnk_x8 = 0x08,
474 ice_pcie_lnk_x12 = 0x0C,
475 ice_pcie_lnk_x16 = 0x10,
476 ice_pcie_lnk_x32 = 0x20,
477 ice_pcie_lnk_width_unknown = 0xff,
478 };
479
480 /* Reset types used to determine which kind of reset was requested. These
481 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
482 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
483 * because its reset source is different than the other types listed.
484 */
485 enum ice_reset_req {
486 ICE_RESET_POR = 0,
487 ICE_RESET_INVAL = 0,
488 ICE_RESET_CORER = 1,
489 ICE_RESET_GLOBR = 2,
490 ICE_RESET_EMPR = 3,
491 ICE_RESET_PFR = 4,
492 };
493
494 /* Bus parameters */
495 struct ice_bus_info {
496 enum ice_pcie_bus_speed speed;
497 enum ice_pcie_link_width width;
498 enum ice_bus_type type;
499 u16 domain_num;
500 u16 device;
501 u8 func;
502 u8 bus_num;
503 };
504
505 /* Flow control (FC) parameters */
506 struct ice_fc_info {
507 enum ice_fc_mode current_mode; /* FC mode in effect */
508 enum ice_fc_mode req_mode; /* FC mode requested by caller */
509 };
510
511 /* Option ROM version information */
512 struct ice_orom_info {
513 u8 major; /* Major version of OROM */
514 u8 patch; /* Patch version of OROM */
515 u16 build; /* Build version of OROM */
516 u32 srev; /* Security revision */
517 };
518
519 /* NVM version information */
520 struct ice_nvm_info {
521 u32 eetrack;
522 u32 srev;
523 u8 major;
524 u8 minor;
525 };
526
527 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
528 * of the flash image.
529 */
530 enum ice_flash_bank {
531 ICE_INVALID_FLASH_BANK,
532 ICE_1ST_FLASH_BANK,
533 ICE_2ND_FLASH_BANK,
534 };
535
536 /* information for accessing NVM, OROM, and Netlist flash banks */
537 struct ice_bank_info {
538 u32 nvm_ptr; /* Pointer to 1st NVM bank */
539 u32 nvm_size; /* Size of NVM bank */
540 u32 orom_ptr; /* Pointer to 1st OROM bank */
541 u32 orom_size; /* Size of OROM bank */
542 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
543 u32 netlist_size; /* Size of Netlist bank */
544 enum ice_flash_bank nvm_bank; /* Active NVM bank */
545 enum ice_flash_bank orom_bank; /* Active OROM bank */
546 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
547 };
548
549 /* Flash Chip Information */
550 struct ice_flash_info {
551 struct ice_orom_info orom; /* Option ROM version info */
552 struct ice_nvm_info nvm; /* NVM version information */
553 struct ice_bank_info banks; /* Flash Bank information */
554 u16 sr_words; /* Shadow RAM size in words */
555 u32 flash_size; /* Size of available flash in bytes */
556 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
557 };
558
559 struct ice_link_default_override_tlv {
560 u8 options;
561 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
562 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
563 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
564 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
565 #define ICE_LINK_OVERRIDE_EN BIT(3)
566 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
567 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
568 u8 phy_config;
569 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
570 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
571 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
572 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
573 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
574 u8 fec_options;
575 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
576 u8 rsvd1;
577 u64 phy_type_low;
578 u64 phy_type_high;
579 };
580
581 #define ICE_NVM_VER_LEN 32
582
583 /* Max number of port to queue branches w.r.t topology */
584 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
585
586 #define ice_for_each_traffic_class(_i) \
587 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
588
589 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
590 * to driver defined policy for default aggregator
591 */
592 #define ICE_INVAL_TEID 0xFFFFFFFF
593 #define ICE_DFLT_AGG_ID 0
594
595 struct ice_sched_node {
596 struct ice_sched_node *parent;
597 struct ice_sched_node *sibling; /* next sibling in the same layer */
598 struct ice_sched_node **children;
599 struct ice_aqc_txsched_elem_data info;
600 u32 agg_id; /* aggregator group ID */
601 u16 vsi_handle;
602 u8 in_use; /* suspended or in use */
603 u8 tx_sched_layer; /* Logical Layer (1-9) */
604 u8 num_children;
605 u8 tc_num;
606 u8 owner;
607 #define ICE_SCHED_NODE_OWNER_LAN 0
608 #define ICE_SCHED_NODE_OWNER_AE 1
609 #define ICE_SCHED_NODE_OWNER_RDMA 2
610 };
611
612 /* Access Macros for Tx Sched Elements data */
613 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
614 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
615 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
616 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
617 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
618 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
619 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
620 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
621 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
622 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
623 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
624
625 struct ice_sched_rl_profile {
626 u32 rate; /* In Kbps */
627 struct ice_aqc_rl_profile_elem info;
628 };
629
630 /* The aggregator type determines if identifier is for a VSI group,
631 * aggregator group, aggregator of queues, or queue group.
632 */
633 enum ice_agg_type {
634 ICE_AGG_TYPE_UNKNOWN = 0,
635 ICE_AGG_TYPE_TC,
636 ICE_AGG_TYPE_AGG, /* aggregator */
637 ICE_AGG_TYPE_VSI,
638 ICE_AGG_TYPE_QG,
639 ICE_AGG_TYPE_Q
640 };
641
642 /* Rate limit types */
643 enum ice_rl_type {
644 ICE_UNKNOWN_BW = 0,
645 ICE_MIN_BW, /* for CIR profile */
646 ICE_MAX_BW, /* for EIR profile */
647 ICE_SHARED_BW /* for shared profile */
648 };
649
650 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
651 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
652 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
653 #define ICE_SCHED_NO_PRIORITY 0
654 #define ICE_SCHED_NO_BW_WT 0
655 #define ICE_SCHED_DFLT_RL_PROF_ID 0
656 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
657 #define ICE_SCHED_DFLT_BW_WT 4
658 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
659 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
660
661 /* Access Macros for Tx Sched RL Profile data */
662 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
663 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
664 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
665 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
666 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
667
668 /* The following tree example shows the naming conventions followed under
669 * ice_port_info struct for default scheduler tree topology.
670 *
671 * A tree on a port
672 * * ---> root node
673 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
674 * * * * * * * * * |
675 * / |
676 * * |
677 * / |-> num_elements (range:1 - 9)
678 * * | implies num_of_layers
679 * / |
680 * (a)* |
681 *
682 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
683 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
684 * need TEID of (a) to add queues.
685 *
686 * This tree
687 * -> has 8 branches (one for each TC)
688 * -> First branch (TC0) has 4 elements
689 * -> has 4 layers
690 * -> (a) is the topmost layer node created by firmware on branch 0
691 *
692 * Note: Above asterisk tree covers only basic terminology and scenario.
693 * Refer to the documentation for more info.
694 */
695
696 /* Data structure for saving BW information */
697 enum ice_bw_type {
698 ICE_BW_TYPE_PRIO,
699 ICE_BW_TYPE_CIR,
700 ICE_BW_TYPE_CIR_WT,
701 ICE_BW_TYPE_EIR,
702 ICE_BW_TYPE_EIR_WT,
703 ICE_BW_TYPE_SHARED,
704 ICE_BW_TYPE_CNT /* This must be last */
705 };
706
707 struct ice_bw {
708 u32 bw;
709 u16 bw_alloc;
710 };
711
712 struct ice_bw_type_info {
713 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
714 u8 generic;
715 struct ice_bw cir_bw;
716 struct ice_bw eir_bw;
717 u32 shared_bw;
718 };
719
720 /* VSI queue context structure for given TC */
721 struct ice_q_ctx {
722 u16 q_handle;
723 u32 q_teid;
724 /* bw_t_info saves queue BW information */
725 struct ice_bw_type_info bw_t_info;
726 };
727
728 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
729 struct ice_sched_vsi_info {
730 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
731 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
732 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
733 /* bw_t_info saves VSI BW information */
734 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
735 };
736
737 /* CEE or IEEE 802.1Qaz ETS Configuration data */
738 struct ice_dcb_ets_cfg {
739 u8 willing;
740 u8 cbs;
741 u8 maxtcs;
742 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
743 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
744 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
745 };
746
747 /* CEE or IEEE 802.1Qaz PFC Configuration data */
748 struct ice_dcb_pfc_cfg {
749 u8 willing;
750 u8 mbc;
751 u8 pfccap;
752 u8 pfcena;
753 };
754
755 /* CEE or IEEE 802.1Qaz Application Priority data */
756 struct ice_dcb_app_priority_table {
757 u16 prot_id;
758 u8 priority;
759 u8 selector;
760 };
761
762 #define ICE_MAX_USER_PRIORITY 8
763 #define ICE_DCBX_MAX_APPS 32
764 #define ICE_LLDPDU_SIZE 1500
765 #define ICE_TLV_STATUS_OPER 0x1
766 #define ICE_TLV_STATUS_SYNC 0x2
767 #define ICE_TLV_STATUS_ERR 0x4
768 #ifndef ICE_APP_PROT_ID_FCOE
769 #define ICE_APP_PROT_ID_FCOE 0x8906
770 #endif /* ICE_APP_PROT_ID_FCOE */
771 #ifndef ICE_APP_PROT_ID_ISCSI
772 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
773 #endif /* ICE_APP_PROT_ID_ISCSI */
774 #ifndef ICE_APP_PROT_ID_ISCSI_860
775 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
776 #endif /* ICE_APP_PROT_ID_ISCSI_860 */
777 #ifndef ICE_APP_PROT_ID_FIP
778 #define ICE_APP_PROT_ID_FIP 0x8914
779 #endif /* ICE_APP_PROT_ID_FIP */
780 #define ICE_APP_SEL_ETHTYPE 0x1
781 #define ICE_APP_SEL_TCPIP 0x2
782 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
783 #define ICE_CEE_APP_SEL_TCPIP 0x1
784
785 struct ice_dcbx_cfg {
786 u32 numapps;
787 u32 tlv_status; /* CEE mode TLV status */
788 struct ice_dcb_ets_cfg etscfg;
789 struct ice_dcb_ets_cfg etsrec;
790 struct ice_dcb_pfc_cfg pfc;
791 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
792 u8 dcbx_mode;
793 #define ICE_DCBX_MODE_CEE 0x1
794 #define ICE_DCBX_MODE_IEEE 0x2
795 u8 app_mode;
796 #define ICE_DCBX_APPS_NON_WILLING 0x1
797 };
798
799 struct ice_qos_cfg {
800 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
801 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
802 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
803 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
804 u8 is_sw_lldp : 1;
805 };
806
807 struct ice_port_info {
808 struct ice_sched_node *root; /* Root Node per Port */
809 struct ice_hw *hw; /* back pointer to HW instance */
810 u32 last_node_teid; /* scheduler last node info */
811 u16 sw_id; /* Initial switch ID belongs to port */
812 u16 pf_vf_num;
813 u8 port_state;
814 #define ICE_SCHED_PORT_STATE_INIT 0x0
815 #define ICE_SCHED_PORT_STATE_READY 0x1
816 u8 lport;
817 #define ICE_LPORT_MASK 0xff
818 u16 dflt_tx_vsi_rule_id;
819 u16 dflt_tx_vsi_num;
820 u16 dflt_rx_vsi_rule_id;
821 u16 dflt_rx_vsi_num;
822 struct ice_fc_info fc;
823 struct ice_mac_info mac;
824 struct ice_phy_info phy;
825 struct ice_lock sched_lock; /* protect access to TXSched tree */
826 struct ice_sched_node *
827 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
828 struct ice_bw_type_info root_node_bw_t_info;
829 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
830 struct ice_qos_cfg qos_cfg;
831 u8 is_vf:1;
832 };
833
834 struct ice_switch_info {
835 struct LIST_HEAD_TYPE vsi_list_map_head;
836 struct ice_sw_recipe *recp_list;
837 u16 prof_res_bm_init;
838 u16 max_used_prof_index;
839
840 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
841 };
842
843 /* Port hardware description */
844 struct ice_hw {
845 u8 *hw_addr;
846 void *back;
847 struct ice_aqc_layer_props *layer_info;
848 struct ice_port_info *port_info;
849 /* 2D Array for each Tx Sched RL Profile type */
850 struct ice_sched_rl_profile **cir_profiles;
851 struct ice_sched_rl_profile **eir_profiles;
852 struct ice_sched_rl_profile **srl_profiles;
853 /* PSM clock frequency for calculating RL profile params */
854 u32 psm_clk_freq;
855 u64 debug_mask; /* BITMAP for debug mask */
856 enum ice_mac_type mac_type;
857
858 u16 fd_ctr_base; /* FD counter base index */
859 /* pci info */
860 u16 device_id;
861 u16 vendor_id;
862 u16 subsystem_device_id;
863 u16 subsystem_vendor_id;
864 u8 revision_id;
865
866 u8 pf_id; /* device profile info */
867
868 u16 max_burst_size; /* driver sets this value */
869
870 /* Tx Scheduler values */
871 u8 num_tx_sched_layers;
872 u8 num_tx_sched_phys_layers;
873 u8 flattened_layers;
874 u8 max_cgds;
875 u8 sw_entry_point_layer;
876 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
877 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
878 /* List contain profile ID(s) and other params per layer */
879 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
880 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
881 u8 evb_veb; /* true for VEB, false for VEPA */
882 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
883 struct ice_bus_info bus;
884 struct ice_flash_info flash;
885 struct ice_hw_dev_caps dev_caps; /* device capabilities */
886 struct ice_hw_func_caps func_caps; /* function capabilities */
887
888 struct ice_switch_info *switch_info; /* switch filter lists */
889
890 /* Control Queue info */
891 struct ice_ctl_q_info adminq;
892 struct ice_ctl_q_info mailboxq;
893 /* Additional function to send AdminQ command */
894 int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc,
895 void *buf, u16 buf_size);
896 void *aq_send_cmd_param;
897 u8 dcf_enabled; /* Device Config Function */
898
899 u8 api_branch; /* API branch version */
900 u8 api_maj_ver; /* API major version */
901 u8 api_min_ver; /* API minor version */
902 u8 api_patch; /* API patch version */
903 u8 fw_branch; /* firmware branch version */
904 u8 fw_maj_ver; /* firmware major version */
905 u8 fw_min_ver; /* firmware minor version */
906 u8 fw_patch; /* firmware patch version */
907 u32 fw_build; /* firmware build number */
908
909 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
910 * register. Used for determining the ITR/INTRL granularity during
911 * initialization.
912 */
913 #define ICE_MAX_AGG_BW_200G 0x0
914 #define ICE_MAX_AGG_BW_100G 0X1
915 #define ICE_MAX_AGG_BW_50G 0x2
916 #define ICE_MAX_AGG_BW_25G 0x3
917 /* ITR granularity for different speeds */
918 #define ICE_ITR_GRAN_ABOVE_25 2
919 #define ICE_ITR_GRAN_MAX_25 4
920 /* ITR granularity in 1 us */
921 u8 itr_gran;
922 /* INTRL granularity for different speeds */
923 #define ICE_INTRL_GRAN_ABOVE_25 4
924 #define ICE_INTRL_GRAN_MAX_25 8
925 /* INTRL granularity in 1 us */
926 u8 intrl_gran;
927
928 u8 ucast_shared; /* true if VSIs can share unicast addr */
929
930 #define ICE_PHY_PER_NAC 1
931 #define ICE_MAX_QUAD 2
932 #define ICE_NUM_QUAD_TYPE 2
933 #define ICE_PORTS_PER_QUAD 4
934 #define ICE_PHY_0_LAST_QUAD 1
935 #define ICE_PORTS_PER_PHY 8
936 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
937
938 /* Active package version (currently active) */
939 struct ice_pkg_ver active_pkg_ver;
940 u32 active_track_id;
941 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
942 u8 active_pkg_in_nvm;
943
944 enum ice_aq_err pkg_dwnld_status;
945
946 /* Driver's package ver - (from the Ice Metadata section) */
947 struct ice_pkg_ver pkg_ver;
948 u8 pkg_name[ICE_PKG_NAME_SIZE];
949
950 /* Driver's Ice segment format version and id (from the Ice seg) */
951 struct ice_pkg_ver ice_seg_fmt_ver;
952 u8 ice_seg_id[ICE_SEG_ID_SIZE];
953
954 /* Pointer to the ice segment */
955 struct ice_seg *seg;
956
957 /* Pointer to allocated copy of pkg memory */
958 u8 *pkg_copy;
959 u32 pkg_size;
960
961 /* tunneling info */
962 struct ice_lock tnl_lock;
963 struct ice_tunnel_table tnl;
964
965 struct ice_acl_tbl *acl_tbl;
966 struct ice_fd_hw_prof **acl_prof;
967 u16 acl_fltr_cnt[ICE_FLTR_PTYPE_MAX];
968 /* HW block tables */
969 struct ice_blk_info blk[ICE_BLK_COUNT];
970 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
971 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
972 /* Flow Director filter info */
973 int fdir_active_fltr;
974
975 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
976 struct LIST_HEAD_TYPE fdir_list_head;
977
978 /* Book-keeping of side-band filter count per flow-type.
979 * This is used to detect and handle input set changes for
980 * respective flow-type.
981 */
982 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
983
984 struct ice_fd_hw_prof **fdir_prof;
985 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
986 struct ice_lock rss_locks; /* protect RSS configuration */
987 struct LIST_HEAD_TYPE rss_list_head;
988 };
989
990 /* Statistics collected by each port, VSI, VEB, and S-channel */
991 struct ice_eth_stats {
992 u64 rx_bytes; /* gorc */
993 u64 rx_unicast; /* uprc */
994 u64 rx_multicast; /* mprc */
995 u64 rx_broadcast; /* bprc */
996 u64 rx_discards; /* rdpc */
997 u64 rx_unknown_protocol; /* rupp */
998 u64 tx_bytes; /* gotc */
999 u64 tx_unicast; /* uptc */
1000 u64 tx_multicast; /* mptc */
1001 u64 tx_broadcast; /* bptc */
1002 u64 tx_discards; /* tdpc */
1003 u64 tx_errors; /* tepc */
1004 u64 rx_no_desc; /* repc */
1005 u64 rx_errors; /* repc */
1006 };
1007
1008 #define ICE_MAX_UP 8
1009
1010 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
1011 struct ice_veb_up_stats {
1012 u64 up_rx_pkts[ICE_MAX_UP];
1013 u64 up_rx_bytes[ICE_MAX_UP];
1014 u64 up_tx_pkts[ICE_MAX_UP];
1015 u64 up_tx_bytes[ICE_MAX_UP];
1016 };
1017
1018 /* Statistics collected by the MAC */
1019 struct ice_hw_port_stats {
1020 /* eth stats collected by the port */
1021 struct ice_eth_stats eth;
1022 /* additional port specific stats */
1023 u64 tx_dropped_link_down; /* tdold */
1024 u64 crc_errors; /* crcerrs */
1025 u64 illegal_bytes; /* illerrc */
1026 u64 error_bytes; /* errbc */
1027 u64 mac_local_faults; /* mlfc */
1028 u64 mac_remote_faults; /* mrfc */
1029 u64 rx_len_errors; /* rlec */
1030 u64 link_xon_rx; /* lxonrxc */
1031 u64 link_xoff_rx; /* lxoffrxc */
1032 u64 link_xon_tx; /* lxontxc */
1033 u64 link_xoff_tx; /* lxofftxc */
1034 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1035 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1036 u64 priority_xon_tx[8]; /* pxontxc[8] */
1037 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1038 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1039 u64 rx_size_64; /* prc64 */
1040 u64 rx_size_127; /* prc127 */
1041 u64 rx_size_255; /* prc255 */
1042 u64 rx_size_511; /* prc511 */
1043 u64 rx_size_1023; /* prc1023 */
1044 u64 rx_size_1522; /* prc1522 */
1045 u64 rx_size_big; /* prc9522 */
1046 u64 rx_undersize; /* ruc */
1047 u64 rx_fragments; /* rfc */
1048 u64 rx_oversize; /* roc */
1049 u64 rx_jabber; /* rjc */
1050 u64 tx_size_64; /* ptc64 */
1051 u64 tx_size_127; /* ptc127 */
1052 u64 tx_size_255; /* ptc255 */
1053 u64 tx_size_511; /* ptc511 */
1054 u64 tx_size_1023; /* ptc1023 */
1055 u64 tx_size_1522; /* ptc1522 */
1056 u64 tx_size_big; /* ptc9522 */
1057 u64 mac_short_pkt_dropped; /* mspdc */
1058 /* flow director stats */
1059 u32 fd_sb_status;
1060 u64 fd_sb_match;
1061 };
1062
1063 enum ice_sw_fwd_act_type {
1064 ICE_FWD_TO_VSI = 0,
1065 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1066 ICE_FWD_TO_Q,
1067 ICE_FWD_TO_QGRP,
1068 ICE_DROP_PACKET,
1069 ICE_INVAL_ACT
1070 };
1071
1072 struct ice_aq_get_set_rss_lut_params {
1073 u16 vsi_handle; /* software VSI handle */
1074 u16 lut_size; /* size of the LUT buffer */
1075 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1076 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1077 u8 global_lut_id; /* only valid when lut_type is global */
1078 };
1079
1080 /* Checksum and Shadow RAM pointers */
1081 #define ICE_SR_NVM_CTRL_WORD 0x00
1082 #define ICE_SR_PHY_ANALOG_PTR 0x04
1083 #define ICE_SR_OPTION_ROM_PTR 0x05
1084 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1085 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1086 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1087 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
1088 #define ICE_SR_EMP_IMAGE_PTR 0x0B
1089 #define ICE_SR_PE_IMAGE_PTR 0x0C
1090 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
1091 #define ICE_SR_MNG_CFG_PTR 0x0E
1092 #define ICE_SR_EMP_MODULE_PTR 0x0F
1093 #define ICE_SR_PBA_BLOCK_PTR 0x16
1094 #define ICE_SR_BOOT_CFG_PTR 0x132
1095 #define ICE_SR_NVM_WOL_CFG 0x19
1096 #define ICE_NVM_OROM_VER_OFF 0x02
1097 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1098 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1099 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1100 #define ICE_SR_NVM_MAP_VER 0x29
1101 #define ICE_SR_NVM_IMAGE_VER 0x2A
1102 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1103 #define ICE_SR_NVM_EETRACK_LO 0x2D
1104 #define ICE_SR_NVM_EETRACK_HI 0x2E
1105 #define ICE_NVM_VER_LO_SHIFT 0
1106 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1107 #define ICE_NVM_VER_HI_SHIFT 12
1108 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1109 #define ICE_OEM_EETRACK_ID 0xffffffff
1110 #define ICE_OROM_VER_PATCH_SHIFT 0
1111 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1112 #define ICE_OROM_VER_BUILD_SHIFT 8
1113 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1114 #define ICE_OROM_VER_SHIFT 24
1115 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1116 #define ICE_SR_VPD_PTR 0x2F
1117 #define ICE_SR_PXE_SETUP_PTR 0x30
1118 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1119 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1120 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1121 #define ICE_SR_VLAN_CFG_PTR 0x37
1122 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1123 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1124 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1125 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1126 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1127 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1128 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1129 #define ICE_SR_PFA_PTR 0x40
1130 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1131 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1132 #define ICE_SR_NVM_BANK_SIZE 0x43
1133 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1134 #define ICE_SR_OROM_BANK_SIZE 0x45
1135 #define ICE_SR_NETLIST_BANK_PTR 0x46
1136 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1137 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1138 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1139 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1140 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1141 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1142
1143 /* CSS Header words */
1144 #define ICE_NVM_CSS_SREV_L 0x14
1145 #define ICE_NVM_CSS_SREV_H 0x15
1146
1147 /* Size in bytes of Option ROM trailer */
1148 #define ICE_NVM_OROM_TRAILER_LENGTH 660
1149
1150 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1151 #define ICE_SR_VPD_SIZE_WORDS 512
1152 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1153 #define ICE_SR_CTRL_WORD_1_S 0x06
1154 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1155 #define ICE_SR_CTRL_WORD_VALID 0x1
1156 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1157 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1158 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1159
1160 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1161
1162 /* Shadow RAM related */
1163 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1164 #define ICE_SR_BUF_ALIGNMENT 4096
1165 #define ICE_SR_WORDS_IN_1KB 512
1166 /* Checksum should be calculated such that after adding all the words,
1167 * including the checksum word itself, the sum should be 0xBABA.
1168 */
1169 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1170
1171 /* Link override related */
1172 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1173 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1174 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1175 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1176 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1177 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1178 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1179 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1180
1181 #define ICE_PBA_FLAG_DFLT 0xFAFA
1182 /* Hash redirection LUT for VSI - maximum array size */
1183 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1184
1185 /*
1186 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1187 * This is needed to determine the BAR0 space for the VFs
1188 */
1189 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1190 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1191 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1192
1193 /* AQ API version for LLDP_FILTER_CONTROL */
1194 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1195 #define ICE_FW_API_LLDP_FLTR_MIN 7
1196 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1197 #endif /* _ICE_TYPE_H_ */
1198