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/f-stack/dpdk/drivers/net/qede/base/
H A Decore_dev_api.h331 u64 ttl0_discard;
335 u64 rx_ucast_pkts;
336 u64 rx_mcast_pkts;
337 u64 rx_bcast_pkts;
344 u64 tx_ucast_pkts;
345 u64 tx_mcast_pkts;
368 u64 rx_jabbers;
370 u64 rx_fragments;
380 u64 brb_discards;
381 u64 rx_mac_bytes;
[all …]
/f-stack/dpdk/drivers/net/atlantic/
H A Datl_types.h36 u64 uprc;
37 u64 mprc;
38 u64 bprc;
39 u64 erpt;
40 u64 uptc;
41 u64 mptc;
42 u64 bptc;
43 u64 erpr;
44 u64 mbtc;
45 u64 bbtc;
[all …]
/f-stack/dpdk/drivers/raw/ifpga/base/
H A Difpga_defines.h108 u64 csr;
127 u64 csr;
138 u64 csr;
148 u64 csr;
185 u64 csr;
201 u64 csr;
215 u64 csr;
227 u64 csr;
241 u64 csr;
266 u64 csr;
[all …]
/f-stack/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_niccfg.h146 u64 tx_discard_vport;
147 u64 rx_discard_vport;
148 u64 tx_err_vport;
155 u64 mac_rx_bad_pkt_num;
156 u64 mac_rx_bad_oct_num;
159 u64 mac_rx_uni_pkt_num;
165 u64 mac_tx_bad_pkt_num;
166 u64 mac_tx_bad_oct_num;
169 u64 mac_tx_uni_pkt_num;
194 u64 mac_rx_pfc_pkt_num;
[all …]
H A Dhinic_pmd_wq.h18 #define WQ_PAGE_ADDR_SIZE sizeof(u64)
21 (u8 *)(*(u64 *)((u64)((wq)->shadow_block_vaddr) + \
37 (u64 *)(((u64)((wqs)->page_vaddr[(wq)->page_idx])) \
41 + (u64)(wq)->block_idx * WQ_BLOCK_SIZE)
44 (u64 *)(((u64)((wqs)->shadow_page_vaddr[(wq)->page_idx])) \
48 (u64 *)(((u64)((cmdq_pages)->cmdq_page_vaddr)) \
52 (((u64)((cmdq_pages)->cmdq_page_paddr)) \
53 + (u64)(wq)->block_idx * CMDQ_BLOCK_SIZE)
56 (u64 *)(((u64)((cmdq_pages)->cmdq_shadow_page_vaddr)) \
96 u64 queue_buf_vaddr;
[all …]
/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-ilk.c395 ilk_rxx_idx_cal.u64 = 0; in cvmx_ilk_rx_cal_conf()
439 ilk_rxx_mem_cal0.u64 = 0; in cvmx_ilk_rx_cal_conf()
440 ilk_rxx_mem_cal1.u64 = 0; in cvmx_ilk_rx_cal_conf()
649 ilk_txx_idx_cal.u64 = 0; in cvmx_ilk_tx_cal_conf()
864 ilk_rxf_idx_pmap.u64 = 0; in cvmx_ilk_reg_dump_rx()
876 ilk_rxx_idx_cal.u64 = 0; in cvmx_ilk_reg_dump_rx()
913 ilk_txx_idx_pmap.u64 = 0; in cvmx_ilk_reg_dump_tx()
927 ilk_txx_idx_cal.u64 = 0; in cvmx_ilk_reg_dump_tx()
982 if (ilk_rxx_int.u64) in cvmx_ilk_runtime_status()
995 if (ilk_gbl_int.u64) in cvmx_ilk_runtime_status()
[all …]
H A Dcvmx-spi.c242 spxx_clk_ctl.u64 = 0; in cvmx_spi_reset_cb()
260 srxx_spi4_calx.u64 = 0; in cvmx_spi_reset_cb()
276 spxx_clk_ctl.u64 = 0; in cvmx_spi_reset_cb()
337 srxx_com_ctl.u64 = 0; in cvmx_spi_calendar_setup_cb()
374 stxx_arb_ctl.u64 = 0; in cvmx_spi_calendar_setup_cb()
395 stxx_spi4_dat.u64 = 0; in cvmx_spi_calendar_setup_cb()
518 spxx_clk_ctl.u64 = 0; in cvmx_spi_training_cb()
597 stxx_com_ctl.u64 = 0; in cvmx_spi_calendar_sync_cb()
651 gmxx_rxx_frm_min.u64 = 0; in cvmx_spi_interface_up_cb()
661 gmxx_rxx_frm_max.u64 = 0; in cvmx_spi_interface_up_cb()
[all …]
H A Dcvmx-ipd.c96 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); in __cvmx_ipd_free_ptr_v1()
101 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in __cvmx_ipd_free_ptr_v1()
109 ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); in __cvmx_ipd_free_ptr_v1()
124 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
125 ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); in __cvmx_ipd_free_ptr_v1()
138 ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); in __cvmx_ipd_free_ptr_v1()
186 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); in __cvmx_ipd_free_ptr_v1()
202 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); in __cvmx_ipd_free_ptr_v2()
207 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in __cvmx_ipd_free_ptr_v2()
215 ipd_next_wqe_ptr.u64 = cvmx_read_csr(CVMX_IPD_NEXT_WQE_PTR); in __cvmx_ipd_free_ptr_v2()
[all …]
H A Dcvmx-pip.h248 uint64_t u64; member
331 pip_qos_vlanx.u64 = 0; in cvmx_pip_config_vlan_qos()
353 pip_qos_diffx.u64 = 0; in cvmx_pip_config_diffserv_qos()
388 pip_stat_ctl.u64 = 0; in cvmx_pip_get_port_status()
390 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); in cvmx_pip_get_port_status()
398 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_X(pknd)); in cvmx_pip_get_port_status()
399 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_X(pknd)); in cvmx_pip_get_port_status()
520 config.u64 = 0; in cvmx_pip_config_crc()
525 pip_crc_ivx.u64 = 0; in cvmx_pip_config_crc()
544 pip_tag_incx.u64 = 0; in cvmx_pip_tag_mask_clear()
[all …]
H A Dcvmx-helper-xaui.c119 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); in __cvmx_helper_xaui_probe()
123 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
133 mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); in __cvmx_helper_xaui_probe()
138 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); in __cvmx_helper_xaui_probe()
142 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_xaui_probe()
161 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_xaui_probe()
163 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe()
175 pko_mem_port_ptrs.u64 = 0; in __cvmx_helper_xaui_probe()
259 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); in __cvmx_helper_xaui_link_init()
363 result.u64 = 0; in __cvmx_helper_xaui_link_get()
[all …]
H A Dcvmx-dma-engine.c120 dmax_ibuff_saddr.u64 = 0; in cvmx_dma_engine_initialize()
145 dma_control.u64 = 0; in cvmx_dma_engine_initialize()
180 dpi_engx_buf.u64 = 0; in cvmx_dma_engine_initialize()
211 dma_control.u64 = 0; in cvmx_dma_engine_initialize()
330 cmds[0] = header.u64; in cvmx_dma_engine_submit()
391 buffers[segments].u64 = 0; in __cvmx_dma_engine_build_internal_pointers()
421 buffers[0].u64 = 0; in __cvmx_dma_engine_build_external_pointers()
426 buffers[1].u64 = address; in __cvmx_dma_engine_build_external_pointers()
435 buffers[1].u64 = address; in __cvmx_dma_engine_build_external_pointers()
437 buffers[2].u64 = address; in __cvmx_dma_engine_build_external_pointers()
[all …]
H A Dcvmx-pcie.c109 pcie_addr.u64 = 0; in cvmx_pcie_get_io_base_address()
116 return pcie_addr.u64; in cvmx_pcie_get_io_base_address()
145 pcie_addr.u64 = 0; in cvmx_pcie_get_mem_base_address()
150 return pcie_addr.u64; in cvmx_pcie_get_mem_base_address()
664 mem_access_subid.u64 = 0; in __cvmx_pcie_rc_initialize_gen1()
1059 if (pemx_bist_status.u64) in __cvmx_pcie_rc_initialize_gen2()
1161 bar1_index.u64 = 0; in __cvmx_pcie_rc_initialize_gen2()
1272 pcie_addr.u64 = 0; in __cvmx_pcie_build_config_addr()
1284 return pcie_addr.u64; in __cvmx_pcie_build_config_addr()
1430 pemx_cfg_rd.u64 = 0; in cvmx_pcie_cfgx_read()
[all …]
H A Dcvmx-ipd.h122 first_skip.u64 = 0; in cvmx_ipd_config()
126 not_first_skip.u64 = 0; in cvmx_ipd_config()
130 size.u64 = 0; in cvmx_ipd_config()
132 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config()
134 first_back_struct.u64 = 0; in cvmx_ipd_config()
138 second_back_struct.u64 = 0; in cvmx_ipd_config()
142 wqe_pool.u64 = 0; in cvmx_ipd_config()
163 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_enable()
182 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable()
192 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); in cvmx_ipd_disable()
[all …]
H A Dcvmx-helper-sgmii.c383 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); in __cvmx_helper_sgmii_hardware_init()
387 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
397 mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); in __cvmx_helper_sgmii_hardware_init()
402 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); in __cvmx_helper_sgmii_hardware_init()
406 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); in __cvmx_helper_sgmii_hardware_init()
465 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_sgmii_probe()
467 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_sgmii_probe()
524 gmxx_txx_append_cfg.u64 = cvmx_read_csr( in __cvmx_helper_sgmii_enable()
529 gmxx_txx_append_cfg.u64); in __cvmx_helper_sgmii_enable()
586 inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); in __cvmx_helper_sgmii_link_get()
[all …]
H A Dcvmx-gpio.h78 multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST); in cvmx_gpio_interrupt_clear()
79 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core)); in cvmx_gpio_interrupt_clear()
98 gpio_int_clr.u64 = 0; in cvmx_gpio_interrupt_clear()
100 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); in cvmx_gpio_interrupt_clear()
131 gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit)); in cvmx_gpio_cfg()
136 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); in cvmx_gpio_cfg()
148 gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT); in cvmx_gpio_read()
161 gpio_tx_clr.u64 = 0; in cvmx_gpio_clear()
163 cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64); in cvmx_gpio_clear()
175 gpio_tx_set.u64 = 0; in cvmx_gpio_set()
[all …]
/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_type.h253 u64 rx_pb_dropped;
262 u64 rx_qp_bytes;
263 u64 tx_qp_bytes;
272 u64 rx_packets;
273 u64 tx_packets;
274 u64 rx_bytes;
275 u64 tx_bytes;
367 u64 rx_up_bytes;
368 u64 tx_up_bytes;
384 u64 rx_qp_bytes;
[all …]
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_hw.h512 u64 mpc;
513 u64 scc;
515 u64 mcc;
518 u64 dc;
520 u64 sec;
541 u64 ruc;
542 u64 rfc;
543 u64 roc;
544 u64 rjc;
548 u64 tor;
[all …]
H A De1000_vf.h136 u64 base_gprc;
137 u64 base_gptc;
156 u64 gprc;
157 u64 gptc;
158 u64 gorc;
159 u64 gotc;
160 u64 mprc;
161 u64 gotlbc;
162 u64 gptlbc;
163 u64 gorlbc;
[all …]
/f-stack/dpdk/drivers/net/igc/base/
H A Digc_hw.h524 u64 mpc;
525 u64 scc;
527 u64 mcc;
530 u64 dc;
532 u64 sec;
553 u64 ruc;
554 u64 rfc;
555 u64 roc;
556 u64 rjc;
560 u64 tor;
[all …]
/f-stack/dpdk/drivers/crypto/nitrox/
H A Dnitrox_hal.c48 pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); in nps_pkt_solicited_port_disable()
50 nitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64); in nps_pkt_solicited_port_disable()
53 pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); in nps_pkt_solicited_port_disable()
81 pkt_in_instr_rsize.u64 = 0; in setup_nps_pkt_input_ring()
88 pkt_in_instr_baoff_dbell.u64 = 0; in setup_nps_pkt_input_ring()
106 pkt_in_instr_ctl.u64 = 0; in setup_nps_pkt_input_ring()
113 pkt_in_instr_ctl.u64 = 0; in setup_nps_pkt_input_ring()
141 pkt_slc_int_levels.u64 = 0; in setup_nps_pkt_solicit_output_port()
174 aqmq_qsz.u64 = 0; in vf_get_vf_config_mode()
177 nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64); in vf_get_vf_config_mode()
[all …]
/f-stack/dpdk/drivers/net/cxgbe/base/
H A Dcommon.h64 u64 tx_frames_65_127;
65 u64 tx_frames_128_255;
66 u64 tx_frames_256_511;
67 u64 tx_frames_512_1023;
68 u64 tx_frames_1024_1518;
69 u64 tx_frames_1519_max;
95 u64 rx_frames_65_127;
96 u64 rx_frames_128_255;
97 u64 rx_frames_256_511;
98 u64 rx_frames_512_1023;
[all …]
/f-stack/dpdk/drivers/net/ena/
H A Dena_ethdev.h76 u64 cnt;
77 u64 bytes;
79 u64 linearize;
81 u64 tx_poll;
82 u64 doorbells;
88 u64 cnt;
89 u64 bytes;
91 u64 bad_csum;
159 u64 rx_drops;
165 u64 dev_stop;
[all …]
/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_vf.h65 u64 base_vfgprc;
66 u64 base_vfgptc;
67 u64 base_vfgorc;
68 u64 base_vfgotc;
69 u64 base_vfmprc;
71 u64 last_vfgprc;
77 u64 vfgprc;
78 u64 vfgptc;
79 u64 vfgorc;
80 u64 vfgotc;
[all …]
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_type.h79 if (((u64)1 << i) & n) in ice_ilog2()
92 static inline u64 round_up_64bit(u64 a, u32 b) in round_up_64bit()
244 u64 phy_type_low;
245 u64 phy_type_high;
283 u64 phy_type_low;
284 u64 phy_type_high;
353 u64 wr_csr_prot;
577 u64 phy_type_low;
578 u64 phy_type_high;
992 u64 rx_bytes; /* gorc */
[all …]
/f-stack/freebsd/mips/cavium/octe/
H A Dethernet-rgmii.c72 if (link_info.u64 == priv->link_info) { in cvm_oct_rgmii_poll()
97 ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); in cvm_oct_rgmii_poll()
99 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in cvm_oct_rgmii_poll()
126 ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); in cvm_oct_rgmii_poll()
128 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in cvm_oct_rgmii_poll()
136 priv->link_info = link_info.u64; in cvm_oct_rgmii_poll()
148 rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS); in cvm_oct_rgmii_rml_interrupt()
164 gmx_rx_int_reg.u64 = 0; in cvm_oct_rgmii_rml_interrupt()
188 gmx_rx_int_reg.u64 = 0; in cvm_oct_rgmii_rml_interrupt()
253 gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface)); in cvm_oct_rgmii_init()
[all …]

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