1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_TYPE_H_ 6 #define _TXGBE_TYPE_H_ 7 8 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP 9 #define TXGBE_DCB_UP_MAX TXGBE_MAX_UP 10 #define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP 11 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 12 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 13 14 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */ 15 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */ 16 #define TXGBE_NUM_POOL (64) 17 #define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 18 #define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 19 #define TXGBE_MAX_UP 8 20 #define TXGBE_MAX_QP (128) 21 #define TXGBE_MAX_UTA 128 22 23 #define TXGBE_ALIGN 128 /* as intel did */ 24 25 #include "txgbe_status.h" 26 #include "txgbe_osdep.h" 27 #include "txgbe_devids.h" 28 29 struct txgbe_thermal_diode_data { 30 s16 temp; 31 s16 alarm_thresh; 32 s16 dalarm_thresh; 33 }; 34 35 struct txgbe_thermal_sensor_data { 36 struct txgbe_thermal_diode_data sensor[1]; 37 }; 38 39 /* Packet buffer allocation strategies */ 40 enum { 41 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 42 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 43 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 44 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 45 }; 46 47 /* Physical layer type */ 48 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0 49 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 50 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002 51 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004 52 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008 53 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010 54 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020 55 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040 56 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080 57 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100 58 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200 59 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400 60 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800 61 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000 62 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000 63 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 64 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 65 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 66 67 #define TXGBE_ATR_HASH_MASK 0x7fff 68 69 enum txgbe_eeprom_type { 70 txgbe_eeprom_unknown = 0, 71 txgbe_eeprom_spi, 72 txgbe_eeprom_flash, 73 txgbe_eeprom_none /* No NVM support */ 74 }; 75 76 enum txgbe_mac_type { 77 txgbe_mac_unknown = 0, 78 txgbe_mac_raptor, 79 txgbe_mac_raptor_vf, 80 txgbe_num_macs 81 }; 82 83 enum txgbe_phy_type { 84 txgbe_phy_unknown = 0, 85 txgbe_phy_none, 86 txgbe_phy_tn, 87 txgbe_phy_aq, 88 txgbe_phy_ext_1g_t, 89 txgbe_phy_cu_mtd, 90 txgbe_phy_cu_unknown, 91 txgbe_phy_qt, 92 txgbe_phy_xaui, 93 txgbe_phy_nl, 94 txgbe_phy_sfp_tyco_passive, 95 txgbe_phy_sfp_unknown_passive, 96 txgbe_phy_sfp_unknown_active, 97 txgbe_phy_sfp_avago, 98 txgbe_phy_sfp_ftl, 99 txgbe_phy_sfp_ftl_active, 100 txgbe_phy_sfp_unknown, 101 txgbe_phy_sfp_intel, 102 txgbe_phy_qsfp_unknown_passive, 103 txgbe_phy_qsfp_unknown_active, 104 txgbe_phy_qsfp_intel, 105 txgbe_phy_qsfp_unknown, 106 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */ 107 txgbe_phy_sgmii, 108 txgbe_phy_fw, 109 txgbe_phy_generic 110 }; 111 112 /* 113 * SFP+ module type IDs: 114 * 115 * ID Module Type 116 * ============= 117 * 0 SFP_DA_CU 118 * 1 SFP_SR 119 * 2 SFP_LR 120 * 3 SFP_DA_CU_CORE0 - chip-specific 121 * 4 SFP_DA_CU_CORE1 - chip-specific 122 * 5 SFP_SR/LR_CORE0 - chip-specific 123 * 6 SFP_SR/LR_CORE1 - chip-specific 124 */ 125 enum txgbe_sfp_type { 126 txgbe_sfp_type_unknown = 0, 127 txgbe_sfp_type_da_cu, 128 txgbe_sfp_type_sr, 129 txgbe_sfp_type_lr, 130 txgbe_sfp_type_da_cu_core0, 131 txgbe_sfp_type_da_cu_core1, 132 txgbe_sfp_type_srlr_core0, 133 txgbe_sfp_type_srlr_core1, 134 txgbe_sfp_type_da_act_lmt_core0, 135 txgbe_sfp_type_da_act_lmt_core1, 136 txgbe_sfp_type_1g_cu_core0, 137 txgbe_sfp_type_1g_cu_core1, 138 txgbe_sfp_type_1g_sx_core0, 139 txgbe_sfp_type_1g_sx_core1, 140 txgbe_sfp_type_1g_lx_core0, 141 txgbe_sfp_type_1g_lx_core1, 142 txgbe_sfp_type_not_present = 0xFFFE, 143 txgbe_sfp_type_not_known = 0xFFFF 144 }; 145 146 enum txgbe_media_type { 147 txgbe_media_type_unknown = 0, 148 txgbe_media_type_fiber, 149 txgbe_media_type_fiber_qsfp, 150 txgbe_media_type_copper, 151 txgbe_media_type_backplane, 152 txgbe_media_type_cx4, 153 txgbe_media_type_virtual 154 }; 155 156 /* Flow Control Settings */ 157 enum txgbe_fc_mode { 158 txgbe_fc_none = 0, 159 txgbe_fc_rx_pause, 160 txgbe_fc_tx_pause, 161 txgbe_fc_full, 162 txgbe_fc_default 163 }; 164 165 /* Smart Speed Settings */ 166 #define TXGBE_SMARTSPEED_MAX_RETRIES 3 167 enum txgbe_smart_speed { 168 txgbe_smart_speed_auto = 0, 169 txgbe_smart_speed_on, 170 txgbe_smart_speed_off 171 }; 172 173 /* PCI bus types */ 174 enum txgbe_bus_type { 175 txgbe_bus_type_unknown = 0, 176 txgbe_bus_type_pci, 177 txgbe_bus_type_pcix, 178 txgbe_bus_type_pci_express, 179 txgbe_bus_type_internal, 180 txgbe_bus_type_reserved 181 }; 182 183 /* PCI bus speeds */ 184 enum txgbe_bus_speed { 185 txgbe_bus_speed_unknown = 0, 186 txgbe_bus_speed_33 = 33, 187 txgbe_bus_speed_66 = 66, 188 txgbe_bus_speed_100 = 100, 189 txgbe_bus_speed_120 = 120, 190 txgbe_bus_speed_133 = 133, 191 txgbe_bus_speed_2500 = 2500, 192 txgbe_bus_speed_5000 = 5000, 193 txgbe_bus_speed_8000 = 8000, 194 txgbe_bus_speed_reserved 195 }; 196 197 /* PCI bus widths */ 198 enum txgbe_bus_width { 199 txgbe_bus_width_unknown = 0, 200 txgbe_bus_width_pcie_x1 = 1, 201 txgbe_bus_width_pcie_x2 = 2, 202 txgbe_bus_width_pcie_x4 = 4, 203 txgbe_bus_width_pcie_x8 = 8, 204 txgbe_bus_width_32 = 32, 205 txgbe_bus_width_64 = 64, 206 txgbe_bus_width_reserved 207 }; 208 209 struct txgbe_hw; 210 211 struct txgbe_addr_filter_info { 212 u32 num_mc_addrs; 213 u32 rar_used_count; 214 u32 mta_in_use; 215 u32 overflow_promisc; 216 bool user_set_promisc; 217 }; 218 219 /* Bus parameters */ 220 struct txgbe_bus_info { 221 s32 (*get_bus_info)(struct txgbe_hw *hw); 222 void (*set_lan_id)(struct txgbe_hw *hw); 223 224 enum txgbe_bus_speed speed; 225 enum txgbe_bus_width width; 226 enum txgbe_bus_type type; 227 228 u16 func; 229 u8 lan_id; 230 u16 instance_id; 231 }; 232 233 /* Flow control parameters */ 234 struct txgbe_fc_info { 235 u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */ 236 u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */ 237 u16 pause_time; /* Flow Control Pause timer */ 238 bool send_xon; /* Flow control send XON */ 239 bool strict_ieee; /* Strict IEEE mode */ 240 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 241 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 242 enum txgbe_fc_mode current_mode; /* FC mode in effect */ 243 enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */ 244 }; 245 246 /* Statistics counters collected by the MAC */ 247 /* PB[] RxTx */ 248 struct txgbe_pb_stats { 249 u64 tx_pb_xon_packets; 250 u64 rx_pb_xon_packets; 251 u64 tx_pb_xoff_packets; 252 u64 rx_pb_xoff_packets; 253 u64 rx_pb_dropped; 254 u64 rx_pb_mbuf_alloc_errors; 255 u64 tx_pb_xon2off_packets; 256 }; 257 258 /* QP[] RxTx */ 259 struct txgbe_qp_stats { 260 u64 rx_qp_packets; 261 u64 tx_qp_packets; 262 u64 rx_qp_bytes; 263 u64 tx_qp_bytes; 264 u64 rx_qp_mc_packets; 265 }; 266 267 struct txgbe_hw_stats { 268 /* MNG RxTx */ 269 u64 mng_bmc2host_packets; 270 u64 mng_host2bmc_packets; 271 /* Basix RxTx */ 272 u64 rx_packets; 273 u64 tx_packets; 274 u64 rx_bytes; 275 u64 tx_bytes; 276 u64 rx_total_bytes; 277 u64 rx_total_packets; 278 u64 tx_total_packets; 279 u64 rx_total_missed_packets; 280 u64 rx_broadcast_packets; 281 u64 tx_broadcast_packets; 282 u64 rx_multicast_packets; 283 u64 tx_multicast_packets; 284 u64 rx_management_packets; 285 u64 tx_management_packets; 286 u64 rx_management_dropped; 287 u64 rx_drop_packets; 288 289 /* Basic Error */ 290 u64 rx_crc_errors; 291 u64 rx_illegal_byte_errors; 292 u64 rx_error_bytes; 293 u64 rx_mac_short_packet_dropped; 294 u64 rx_length_errors; 295 u64 rx_undersize_errors; 296 u64 rx_fragment_errors; 297 u64 rx_oversize_errors; 298 u64 rx_jabber_errors; 299 u64 rx_l3_l4_xsum_error; 300 u64 mac_local_errors; 301 u64 mac_remote_errors; 302 303 /* Flow Director */ 304 u64 flow_director_added_filters; 305 u64 flow_director_removed_filters; 306 u64 flow_director_filter_add_errors; 307 u64 flow_director_filter_remove_errors; 308 u64 flow_director_matched_filters; 309 u64 flow_director_missed_filters; 310 311 /* FCoE */ 312 u64 rx_fcoe_crc_errors; 313 u64 rx_fcoe_mbuf_allocation_errors; 314 u64 rx_fcoe_dropped; 315 u64 rx_fcoe_packets; 316 u64 tx_fcoe_packets; 317 u64 rx_fcoe_bytes; 318 u64 tx_fcoe_bytes; 319 u64 rx_fcoe_no_ddp; 320 u64 rx_fcoe_no_ddp_ext_buff; 321 322 /* MACSEC */ 323 u64 tx_macsec_pkts_untagged; 324 u64 tx_macsec_pkts_encrypted; 325 u64 tx_macsec_pkts_protected; 326 u64 tx_macsec_octets_encrypted; 327 u64 tx_macsec_octets_protected; 328 u64 rx_macsec_pkts_untagged; 329 u64 rx_macsec_pkts_badtag; 330 u64 rx_macsec_pkts_nosci; 331 u64 rx_macsec_pkts_unknownsci; 332 u64 rx_macsec_octets_decrypted; 333 u64 rx_macsec_octets_validated; 334 u64 rx_macsec_sc_pkts_unchecked; 335 u64 rx_macsec_sc_pkts_delayed; 336 u64 rx_macsec_sc_pkts_late; 337 u64 rx_macsec_sa_pkts_ok; 338 u64 rx_macsec_sa_pkts_invalid; 339 u64 rx_macsec_sa_pkts_notvalid; 340 u64 rx_macsec_sa_pkts_unusedsa; 341 u64 rx_macsec_sa_pkts_notusingsa; 342 343 /* MAC RxTx */ 344 u64 rx_size_64_packets; 345 u64 rx_size_65_to_127_packets; 346 u64 rx_size_128_to_255_packets; 347 u64 rx_size_256_to_511_packets; 348 u64 rx_size_512_to_1023_packets; 349 u64 rx_size_1024_to_max_packets; 350 u64 tx_size_64_packets; 351 u64 tx_size_65_to_127_packets; 352 u64 tx_size_128_to_255_packets; 353 u64 tx_size_256_to_511_packets; 354 u64 tx_size_512_to_1023_packets; 355 u64 tx_size_1024_to_max_packets; 356 357 /* Flow Control */ 358 u64 tx_xon_packets; 359 u64 rx_xon_packets; 360 u64 tx_xoff_packets; 361 u64 rx_xoff_packets; 362 363 /* PB[] RxTx */ 364 struct { 365 u64 rx_up_packets; 366 u64 tx_up_packets; 367 u64 rx_up_bytes; 368 u64 tx_up_bytes; 369 u64 rx_up_drop_packets; 370 371 u64 tx_up_xon_packets; 372 u64 rx_up_xon_packets; 373 u64 tx_up_xoff_packets; 374 u64 rx_up_xoff_packets; 375 u64 rx_up_dropped; 376 u64 rx_up_mbuf_alloc_errors; 377 u64 tx_up_xon2off_packets; 378 } up[TXGBE_MAX_UP]; 379 380 /* QP[] RxTx */ 381 struct { 382 u64 rx_qp_packets; 383 u64 tx_qp_packets; 384 u64 rx_qp_bytes; 385 u64 tx_qp_bytes; 386 u64 rx_qp_mc_packets; 387 } qp[TXGBE_MAX_QP]; 388 389 }; 390 391 /* iterator type for walking multicast address lists */ 392 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr, 393 u32 *vmdq); 394 395 struct txgbe_link_info { 396 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val); 397 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 398 u16 *val); 399 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val); 400 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 401 u16 val); 402 403 u8 addr; 404 }; 405 406 struct txgbe_rom_info { 407 s32 (*init_params)(struct txgbe_hw *hw); 408 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data); 409 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data); 410 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 411 void *data); 412 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data); 413 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 414 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data); 415 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data); 416 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 417 void *data); 418 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data); 419 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 420 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val); 421 s32 (*update_checksum)(struct txgbe_hw *hw); 422 s32 (*calc_checksum)(struct txgbe_hw *hw); 423 424 enum txgbe_eeprom_type type; 425 u32 semaphore_delay; 426 u16 word_size; 427 u16 address_bits; 428 u16 word_page_size; 429 u16 ctrl_word_3; 430 431 u32 sw_addr; 432 }; 433 434 struct txgbe_flash_info { 435 u32 semaphore_delay; 436 u32 dword_size; 437 u16 address_bits; 438 }; 439 440 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 441 struct txgbe_mac_info { 442 s32 (*init_hw)(struct txgbe_hw *hw); 443 s32 (*reset_hw)(struct txgbe_hw *hw); 444 s32 (*start_hw)(struct txgbe_hw *hw); 445 s32 (*stop_hw)(struct txgbe_hw *hw); 446 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw); 447 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr); 448 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 449 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 450 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps); 451 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix, 452 u16 *wwpn_prefix); 453 s32 (*setup_sfp)(struct txgbe_hw *hw); 454 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval); 455 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw); 456 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw); 457 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw); 458 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw); 459 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask); 460 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask); 461 u64 (*autoc_read)(struct txgbe_hw *hw); 462 void (*autoc_write)(struct txgbe_hw *hw, u64 value); 463 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value); 464 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value); 465 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api); 466 467 /* Link */ 468 void (*disable_tx_laser)(struct txgbe_hw *hw); 469 void (*enable_tx_laser)(struct txgbe_hw *hw); 470 void (*flap_tx_laser)(struct txgbe_hw *hw); 471 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed, 472 bool autoneg_wait_to_complete); 473 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed, 474 bool autoneg_wait_to_complete); 475 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, 476 bool *link_up, bool link_up_wait_to_complete); 477 s32 (*get_link_capabilities)(struct txgbe_hw *hw, 478 u32 *speed, bool *autoneg); 479 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed); 480 481 /* Packet Buffer manipulation */ 482 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom, 483 int strategy); 484 485 /* LED */ 486 s32 (*led_on)(struct txgbe_hw *hw, u32 index); 487 s32 (*led_off)(struct txgbe_hw *hw, u32 index); 488 489 /* RAR, Multicast, VLAN */ 490 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 491 u32 enable_addr); 492 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr); 493 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index); 494 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 495 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 496 s32 (*init_rx_addrs)(struct txgbe_hw *hw); 497 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list, 498 u32 mc_addr_count, 499 txgbe_mc_addr_itr func, bool clear); 500 s32 (*clear_vfta)(struct txgbe_hw *hw); 501 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan, 502 u32 vind, bool vlan_on, bool vlvf_bypass); 503 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind, 504 bool vlan_on, u32 *vfta_delta, u32 vfta, 505 bool vlvf_bypass); 506 s32 (*init_uta_tables)(struct txgbe_hw *hw); 507 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf); 508 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw, 509 bool enable, int vf); 510 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode); 511 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size); 512 513 /* Flow Control */ 514 s32 (*fc_enable)(struct txgbe_hw *hw); 515 s32 (*setup_fc)(struct txgbe_hw *hw); 516 void (*fc_autoneg)(struct txgbe_hw *hw); 517 518 /* Manageability interface */ 519 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, 520 u8 ver, u16 len, const char *driver_ver); 521 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw); 522 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw); 523 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map); 524 void (*disable_rx)(struct txgbe_hw *hw); 525 void (*enable_rx)(struct txgbe_hw *hw); 526 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw, 527 bool enable, int vf); 528 s32 (*dmac_update_tcs)(struct txgbe_hw *hw); 529 s32 (*dmac_config_tcs)(struct txgbe_hw *hw); 530 s32 (*dmac_config)(struct txgbe_hw *hw); 531 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee); 532 533 enum txgbe_mac_type type; 534 u8 addr[ETH_ADDR_LEN]; 535 u8 perm_addr[ETH_ADDR_LEN]; 536 u8 san_addr[ETH_ADDR_LEN]; 537 /* prefix for World Wide Node Name (WWNN) */ 538 u16 wwnn_prefix; 539 /* prefix for World Wide Port Name (WWPN) */ 540 u16 wwpn_prefix; 541 #define TXGBE_MAX_MTA 128 542 u32 mta_shadow[TXGBE_MAX_MTA]; 543 s32 mc_filter_type; 544 u32 mcft_size; 545 u32 vft_size; 546 u32 num_rar_entries; 547 u32 rx_pb_size; 548 u32 max_tx_queues; 549 u32 max_rx_queues; 550 u8 san_mac_rar_index; 551 bool get_link_status; 552 u64 orig_autoc; /* cached value of AUTOC */ 553 bool orig_link_settings_stored; 554 bool autotry_restart; 555 u8 flags; 556 struct txgbe_thermal_sensor_data thermal_sensor_data; 557 bool set_lben; 558 u32 max_link_up_time; 559 }; 560 561 struct txgbe_phy_info { 562 u32 (*get_media_type)(struct txgbe_hw *hw); 563 s32 (*identify)(struct txgbe_hw *hw); 564 s32 (*identify_sfp)(struct txgbe_hw *hw); 565 s32 (*init)(struct txgbe_hw *hw); 566 s32 (*reset)(struct txgbe_hw *hw); 567 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr, 568 u32 device_type, u16 *phy_data); 569 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr, 570 u32 device_type, u16 phy_data); 571 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 572 u32 device_type, u16 *phy_data); 573 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 574 u32 device_type, u16 phy_data); 575 s32 (*setup_link)(struct txgbe_hw *hw); 576 s32 (*setup_internal_link)(struct txgbe_hw *hw); 577 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed, 578 bool autoneg_wait_to_complete); 579 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up); 580 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 581 u8 dev_addr, u8 *data); 582 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 583 u8 dev_addr, u8 data); 584 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset, 585 u8 *sff8472_data); 586 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 587 u8 *eeprom_data); 588 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 589 u8 eeprom_data); 590 s32 (*check_overtemp)(struct txgbe_hw *hw); 591 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on); 592 s32 (*handle_lasi)(struct txgbe_hw *hw); 593 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 594 u8 *value); 595 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 596 u8 value); 597 598 enum txgbe_phy_type type; 599 u32 addr; 600 u32 id; 601 enum txgbe_sfp_type sfp_type; 602 bool sfp_setup_needed; 603 u32 revision; 604 u32 media_type; 605 u32 phy_semaphore_mask; 606 bool reset_disable; 607 u32 autoneg_advertised; 608 u32 speeds_supported; 609 enum txgbe_smart_speed smart_speed; 610 bool smart_speed_active; 611 bool multispeed_fiber; 612 bool qsfp_shared_i2c_bus; 613 u32 nw_mng_if_sel; 614 u32 link_mode; 615 }; 616 617 struct txgbe_mbx_stats { 618 u32 msgs_tx; 619 u32 msgs_rx; 620 621 u32 acks; 622 u32 reqs; 623 u32 rsts; 624 }; 625 626 struct txgbe_mbx_info { 627 void (*init_params)(struct txgbe_hw *hw); 628 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 629 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 630 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 631 u16 mbx_id); 632 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 633 u16 mbx_id); 634 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id); 635 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id); 636 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id); 637 638 struct txgbe_mbx_stats stats; 639 u32 timeout; 640 u32 usec_delay; 641 u16 size; 642 }; 643 644 enum txgbe_isb_idx { 645 TXGBE_ISB_HEADER, 646 TXGBE_ISB_MISC, 647 TXGBE_ISB_VEC0, 648 TXGBE_ISB_VEC1, 649 TXGBE_ISB_MAX 650 }; 651 652 struct txgbe_hw { 653 void IOMEM *hw_addr; 654 void *back; 655 struct txgbe_mac_info mac; 656 struct txgbe_addr_filter_info addr_ctrl; 657 struct txgbe_fc_info fc; 658 struct txgbe_phy_info phy; 659 struct txgbe_link_info link; 660 struct txgbe_rom_info rom; 661 struct txgbe_flash_info flash; 662 struct txgbe_bus_info bus; 663 struct txgbe_mbx_info mbx; 664 u16 device_id; 665 u16 vendor_id; 666 u16 subsystem_device_id; 667 u16 subsystem_vendor_id; 668 u8 revision_id; 669 bool adapter_stopped; 670 bool allow_unsupported_sfp; 671 bool need_crosstalk_fix; 672 673 uint64_t isb_dma; 674 void IOMEM *isb_mem; 675 u16 nb_rx_queues; 676 u16 nb_tx_queues; 677 678 u32 mode; 679 enum txgbe_link_status { 680 TXGBE_LINK_STATUS_NONE = 0, 681 TXGBE_LINK_STATUS_KX, 682 TXGBE_LINK_STATUS_KX4 683 } link_status; 684 enum txgbe_reset_type { 685 TXGBE_LAN_RESET = 0, 686 TXGBE_SW_RESET, 687 TXGBE_GLOBAL_RESET 688 } reset_type; 689 690 u32 q_rx_regs[128 * 4]; 691 u32 q_tx_regs[128 * 4]; 692 bool offset_loaded; 693 struct { 694 u64 rx_qp_packets; 695 u64 tx_qp_packets; 696 u64 rx_qp_bytes; 697 u64 tx_qp_bytes; 698 u64 rx_qp_mc_packets; 699 } qp_last[TXGBE_MAX_QP]; 700 }; 701 702 #include "txgbe_regs.h" 703 #include "txgbe_dummy.h" 704 705 #endif /* _TXGBE_TYPE_H_ */ 706