1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_RXTX_H_ 6 #define _TXGBE_RXTX_H_ 7 8 /***************************************************************************** 9 * Receive Descriptor 10 *****************************************************************************/ 11 struct txgbe_rx_desc { 12 struct { 13 union { 14 __le32 dw0; 15 struct { 16 __le16 pkt; 17 __le16 hdr; 18 } lo; 19 }; 20 union { 21 __le32 dw1; 22 struct { 23 __le16 ipid; 24 __le16 csum; 25 } hi; 26 }; 27 } qw0; /* also as r.pkt_addr */ 28 struct { 29 union { 30 __le32 dw2; 31 struct { 32 __le32 status; 33 } lo; 34 }; 35 union { 36 __le32 dw3; 37 struct { 38 __le16 len; 39 __le16 tag; 40 } hi; 41 }; 42 } qw1; /* also as r.hdr_addr */ 43 }; 44 45 /* @txgbe_rx_desc.qw0 */ 46 #define TXGBE_RXD_PKTADDR(rxd, v) \ 47 (((volatile __le64 *)(rxd))[0] = cpu_to_le64(v)) 48 49 /* @txgbe_rx_desc.qw1 */ 50 #define TXGBE_RXD_HDRADDR(rxd, v) \ 51 (((volatile __le64 *)(rxd))[1] = cpu_to_le64(v)) 52 53 /* @txgbe_rx_desc.dw0 */ 54 #define TXGBE_RXD_RSSTYPE(dw) RS(dw, 0, 0xF) 55 #define TXGBE_RSSTYPE_NONE 0 56 #define TXGBE_RSSTYPE_IPV4TCP 1 57 #define TXGBE_RSSTYPE_IPV4 2 58 #define TXGBE_RSSTYPE_IPV6TCP 3 59 #define TXGBE_RSSTYPE_IPV4SCTP 4 60 #define TXGBE_RSSTYPE_IPV6 5 61 #define TXGBE_RSSTYPE_IPV6SCTP 6 62 #define TXGBE_RSSTYPE_IPV4UDP 7 63 #define TXGBE_RSSTYPE_IPV6UDP 8 64 #define TXGBE_RSSTYPE_FDIR 15 65 #define TXGBE_RXD_SECTYPE(dw) RS(dw, 4, 0x3) 66 #define TXGBE_RXD_SECTYPE_NONE LS(0, 4, 0x3) 67 #define TXGBE_RXD_SECTYPE_LINKSEC LS(1, 4, 0x3) 68 #define TXGBE_RXD_SECTYPE_IPSECESP LS(2, 4, 0x3) 69 #define TXGBE_RXD_SECTYPE_IPSECAH LS(3, 4, 0x3) 70 #define TXGBE_RXD_TPIDSEL(dw) RS(dw, 6, 0x7) 71 #define TXGBE_RXD_PTID(dw) RS(dw, 9, 0xFF) 72 #define TXGBE_RXD_RSCCNT(dw) RS(dw, 17, 0xF) 73 #define TXGBE_RXD_HDRLEN(dw) RS(dw, 21, 0x3FF) 74 #define TXGBE_RXD_SPH MS(31, 0x1) 75 76 /* @txgbe_rx_desc.dw1 */ 77 /** bit 0-31, as rss hash when **/ 78 #define TXGBE_RXD_RSSHASH(rxd) ((rxd)->qw0.dw1) 79 80 /** bit 0-31, as ip csum when **/ 81 #define TXGBE_RXD_IPID(rxd) ((rxd)->qw0.hi.ipid) 82 #define TXGBE_RXD_CSUM(rxd) ((rxd)->qw0.hi.csum) 83 84 /** bit 0-31, as fdir id when **/ 85 #define TXGBE_RXD_FDIRID(rxd) ((rxd)->qw0.hi.dw1) 86 87 /* @txgbe_rx_desc.dw2 */ 88 #define TXGBE_RXD_STATUS(rxd) ((rxd)->qw1.lo.status) 89 /** bit 0-1 **/ 90 #define TXGBE_RXD_STAT_DD MS(0, 0x1) /* Descriptor Done */ 91 #define TXGBE_RXD_STAT_EOP MS(1, 0x1) /* End of Packet */ 92 /** bit 2-31, when EOP=0 **/ 93 #define TXGBE_RXD_NEXTP_RESV(v) LS(v, 2, 0x3) 94 #define TXGBE_RXD_NEXTP(dw) RS(dw, 4, 0xFFFF) /* Next Descriptor */ 95 /** bit 2-31, when EOP=1 **/ 96 #define TXGBE_RXD_PKT_CLS_MASK MS(2, 0x7) /* Packet Class */ 97 #define TXGBE_RXD_PKT_CLS_TC_RSS LS(0, 2, 0x7) /* RSS Hash */ 98 #define TXGBE_RXD_PKT_CLS_FLM LS(1, 2, 0x7) /* FDir Match */ 99 #define TXGBE_RXD_PKT_CLS_SYN LS(2, 2, 0x7) /* TCP Sync */ 100 #define TXGBE_RXD_PKT_CLS_5TUPLE LS(3, 2, 0x7) /* 5 Tuple */ 101 #define TXGBE_RXD_PKT_CLS_ETF LS(4, 2, 0x7) /* Ethertype Filter */ 102 #define TXGBE_RXD_STAT_VLAN MS(5, 0x1) /* IEEE VLAN Packet */ 103 #define TXGBE_RXD_STAT_UDPCS MS(6, 0x1) /* UDP xsum calculated */ 104 #define TXGBE_RXD_STAT_L4CS MS(7, 0x1) /* L4 xsum calculated */ 105 #define TXGBE_RXD_STAT_IPCS MS(8, 0x1) /* IP xsum calculated */ 106 #define TXGBE_RXD_STAT_PIF MS(9, 0x1) /* Non-unicast address */ 107 #define TXGBE_RXD_STAT_EIPCS MS(10, 0x1) /* Encap IP xsum calculated */ 108 #define TXGBE_RXD_STAT_VEXT MS(11, 0x1) /* Multi-VLAN */ 109 #define TXGBE_RXD_STAT_IPV6EX MS(12, 0x1) /* IPv6 with option header */ 110 #define TXGBE_RXD_STAT_LLINT MS(13, 0x1) /* Pkt caused LLI */ 111 #define TXGBE_RXD_STAT_1588 MS(14, 0x1) /* IEEE1588 Time Stamp */ 112 #define TXGBE_RXD_STAT_SECP MS(15, 0x1) /* Security Processing */ 113 #define TXGBE_RXD_STAT_LB MS(16, 0x1) /* Loopback Status */ 114 /*** bit 17-30, when PTYPE=IP ***/ 115 #define TXGBE_RXD_STAT_BMC MS(17, 0x1) /* PTYPE=IP, BMC status */ 116 #define TXGBE_RXD_ERR_FDIR_LEN MS(20, 0x1) /* FDIR Length error */ 117 #define TXGBE_RXD_ERR_FDIR_DROP MS(21, 0x1) /* FDIR Drop error */ 118 #define TXGBE_RXD_ERR_FDIR_COLL MS(22, 0x1) /* FDIR Collision error */ 119 #define TXGBE_RXD_ERR_HBO MS(23, 0x1) /* Header Buffer Overflow */ 120 #define TXGBE_RXD_ERR_EIPCS MS(26, 0x1) /* Encap IP header error */ 121 #define TXGBE_RXD_ERR_SECERR MS(27, 0x1) /* macsec or ipsec error */ 122 #define TXGBE_RXD_ERR_RXE MS(29, 0x1) /* Any MAC Error */ 123 #define TXGBE_RXD_ERR_L4CS MS(30, 0x1) /* TCP/UDP xsum error */ 124 #define TXGBE_RXD_ERR_IPCS MS(31, 0x1) /* IP xsum error */ 125 #define TXGBE_RXD_ERR_CSUM(dw) RS(dw, 30, 0x3) 126 /*** bit 17-30, when PTYPE=FCOE ***/ 127 #define TXGBE_RXD_STAT_FCOEFS MS(17, 0x1) /* PTYPE=FCOE, FCoE EOF/SOF */ 128 #define TXGBE_RXD_FCSTAT_MASK MS(18, 0x3) /* FCoE Pkt Stat */ 129 #define TXGBE_RXD_FCSTAT_NOMTCH LS(0, 18, 0x3) /* No Ctxt Match */ 130 #define TXGBE_RXD_FCSTAT_NODDP LS(1, 18, 0x3) /* Ctxt w/o DDP */ 131 #define TXGBE_RXD_FCSTAT_FCPRSP LS(2, 18, 0x3) /* Recv. FCP_RSP */ 132 #define TXGBE_RXD_FCSTAT_DDP LS(3, 18, 0x3) /* Ctxt w/ DDP */ 133 #define TXGBE_RXD_FCERR_MASK MS(20, 0x7) /* FCERR */ 134 #define TXGBE_RXD_FCERR_0 LS(0, 20, 0x7) 135 #define TXGBE_RXD_FCERR_1 LS(1, 20, 0x7) 136 #define TXGBE_RXD_FCERR_2 LS(2, 20, 0x7) 137 #define TXGBE_RXD_FCERR_3 LS(3, 20, 0x7) 138 #define TXGBE_RXD_FCERR_4 LS(4, 20, 0x7) 139 #define TXGBE_RXD_FCERR_5 LS(5, 20, 0x7) 140 #define TXGBE_RXD_FCERR_6 LS(6, 20, 0x7) 141 #define TXGBE_RXD_FCERR_7 LS(7, 20, 0x7) 142 143 /* @txgbe_rx_desc.dw3 */ 144 #define TXGBE_RXD_LENGTH(rxd) ((rxd)->qw1.hi.len) 145 #define TXGBE_RXD_VLAN(rxd) ((rxd)->qw1.hi.tag) 146 147 /***************************************************************************** 148 * Transmit Descriptor 149 *****************************************************************************/ 150 /** 151 * Transmit Context Descriptor (TXGBE_TXD_TYP=CTXT) 152 **/ 153 struct txgbe_tx_ctx_desc { 154 __le32 dw0; /* w.vlan_macip_lens */ 155 __le32 dw1; /* w.seqnum_seed */ 156 __le32 dw2; /* w.type_tucmd_mlhl */ 157 __le32 dw3; /* w.mss_l4len_idx */ 158 }; 159 160 /* @txgbe_tx_ctx_desc.dw0 */ 161 #define TXGBE_TXD_IPLEN(v) LS(v, 0, 0x1FF) /* ip/fcoe header end */ 162 #define TXGBE_TXD_MACLEN(v) LS(v, 9, 0x7F) /* desc mac len */ 163 #define TXGBE_TXD_VLAN(v) LS(v, 16, 0xFFFF) /* vlan tag */ 164 165 /* @txgbe_tx_ctx_desc.dw1 */ 166 /*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=0 ***/ 167 #define TXGBE_TXD_IPSEC_SAIDX(v) LS(v, 0, 0x3FF) /* ipsec SA index */ 168 #define TXGBE_TXD_ETYPE(v) LS(v, 11, 0x1) /* tunnel type */ 169 #define TXGBE_TXD_ETYPE_UDP LS(0, 11, 0x1) 170 #define TXGBE_TXD_ETYPE_GRE LS(1, 11, 0x1) 171 #define TXGBE_TXD_EIPLEN(v) LS(v, 12, 0x7F) /* tunnel ip header */ 172 #define TXGBE_TXD_DTYP_FCOE MS(16, 0x1) /* FCoE/IP descriptor */ 173 #define TXGBE_TXD_ETUNLEN(v) LS(v, 21, 0xFF) /* tunnel header */ 174 #define TXGBE_TXD_DECTTL(v) LS(v, 29, 0xF) /* decrease ip TTL */ 175 /*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=1 ***/ 176 #define TXGBE_TXD_FCOEF_EOF_MASK MS(10, 0x3) /* FC EOF index */ 177 #define TXGBE_TXD_FCOEF_EOF_N LS(0, 10, 0x3) /* EOFn */ 178 #define TXGBE_TXD_FCOEF_EOF_T LS(1, 10, 0x3) /* EOFt */ 179 #define TXGBE_TXD_FCOEF_EOF_NI LS(2, 10, 0x3) /* EOFni */ 180 #define TXGBE_TXD_FCOEF_EOF_A LS(3, 10, 0x3) /* EOFa */ 181 #define TXGBE_TXD_FCOEF_SOF MS(12, 0x1) /* FC SOF index */ 182 #define TXGBE_TXD_FCOEF_PARINC MS(13, 0x1) /* Rel_Off in F_CTL */ 183 #define TXGBE_TXD_FCOEF_ORIE MS(14, 0x1) /* orientation end */ 184 #define TXGBE_TXD_FCOEF_ORIS MS(15, 0x1) /* orientation start */ 185 186 /* @txgbe_tx_ctx_desc.dw2 */ 187 #define TXGBE_TXD_IPSEC_ESPLEN(v) LS(v, 1, 0x1FF) /* ipsec ESP length */ 188 #define TXGBE_TXD_SNAP MS(10, 0x1) /* SNAP indication */ 189 #define TXGBE_TXD_TPID_SEL(v) LS(v, 11, 0x7) /* vlan tag index */ 190 #define TXGBE_TXD_IPSEC_ESP MS(14, 0x1) /* ipsec type: esp=1 ah=0 */ 191 #define TXGBE_TXD_IPSEC_ESPENC MS(15, 0x1) /* ESP encrypt */ 192 #define TXGBE_TXD_CTXT MS(20, 0x1) /* context descriptor */ 193 #define TXGBE_TXD_PTID(v) LS(v, 24, 0xFF) /* packet type */ 194 /* @txgbe_tx_ctx_desc.dw3 */ 195 #define TXGBE_TXD_DD MS(0, 0x1) /* descriptor done */ 196 #define TXGBE_TXD_IDX(v) LS(v, 4, 0x1) /* ctxt desc index */ 197 #define TXGBE_TXD_L4LEN(v) LS(v, 8, 0xFF) /* l4 header length */ 198 #define TXGBE_TXD_MSS(v) LS(v, 16, 0xFFFF) /* l4 MSS */ 199 200 /** 201 * Transmit Data Descriptor (TXGBE_TXD_TYP=DATA) 202 **/ 203 struct txgbe_tx_desc { 204 __le64 qw0; /* r.buffer_addr , w.reserved */ 205 __le32 dw2; /* r.cmd_type_len, w.nxtseq_seed */ 206 __le32 dw3; /* r.olinfo_status, w.status */ 207 }; 208 /* @txgbe_tx_desc.qw0 */ 209 210 /* @txgbe_tx_desc.dw2 */ 211 #define TXGBE_TXD_DATLEN(v) ((0xFFFF & (v))) /* data buffer length */ 212 #define TXGBE_TXD_1588 ((0x1) << 19) /* IEEE1588 time stamp */ 213 #define TXGBE_TXD_DATA ((0x0) << 20) /* data descriptor */ 214 #define TXGBE_TXD_EOP ((0x1) << 24) /* End of Packet */ 215 #define TXGBE_TXD_FCS ((0x1) << 25) /* Insert FCS */ 216 #define TXGBE_TXD_LINKSEC ((0x1) << 26) /* Insert LinkSec */ 217 #define TXGBE_TXD_ECU ((0x1) << 28) /* forward to ECU */ 218 #define TXGBE_TXD_CNTAG ((0x1) << 29) /* insert CN tag */ 219 #define TXGBE_TXD_VLE ((0x1) << 30) /* insert VLAN tag */ 220 #define TXGBE_TXD_TSE ((0x1) << 31) /* transmit segmentation */ 221 222 #define TXGBE_TXD_FLAGS (TXGBE_TXD_FCS | TXGBE_TXD_EOP) 223 224 /* @txgbe_tx_desc.dw3 */ 225 #define TXGBE_TXD_DD_UNUSED TXGBE_TXD_DD 226 #define TXGBE_TXD_IDX_UNUSED(v) TXGBE_TXD_IDX(v) 227 #define TXGBE_TXD_CC ((0x1) << 7) /* check context */ 228 #define TXGBE_TXD_IPSEC ((0x1) << 8) /* request ipsec offload */ 229 #define TXGBE_TXD_L4CS ((0x1) << 9) /* insert TCP/UDP/SCTP csum */ 230 #define TXGBE_TXD_IPCS ((0x1) << 10) /* insert IPv4 csum */ 231 #define TXGBE_TXD_EIPCS ((0x1) << 11) /* insert outer IP csum */ 232 #define TXGBE_TXD_MNGFLT ((0x1) << 12) /* enable management filter */ 233 #define TXGBE_TXD_PAYLEN(v) ((0x7FFFF & (v)) << 13) /* payload length */ 234 235 #define RTE_PMD_TXGBE_TX_MAX_BURST 32 236 #define RTE_PMD_TXGBE_RX_MAX_BURST 32 237 #define RTE_TXGBE_TX_MAX_FREE_BUF_SZ 64 238 239 #define RX_RING_SZ ((TXGBE_RING_DESC_MAX + RTE_PMD_TXGBE_RX_MAX_BURST) * \ 240 sizeof(struct txgbe_rx_desc)) 241 242 #define rte_packet_prefetch(p) rte_prefetch1(p) 243 244 #define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS 10 245 #define RTE_TXGBE_WAIT_100_US 100 246 247 #define TXGBE_TX_MAX_SEG 40 248 249 /** 250 * Structure associated with each descriptor of the RX ring of a RX queue. 251 */ 252 struct txgbe_rx_entry { 253 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */ 254 }; 255 256 struct txgbe_scattered_rx_entry { 257 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */ 258 }; 259 260 /** 261 * Structure associated with each descriptor of the TX ring of a TX queue. 262 */ 263 struct txgbe_tx_entry { 264 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ 265 uint16_t next_id; /**< Index of next descriptor in ring. */ 266 uint16_t last_id; /**< Index of last scattered descriptor. */ 267 }; 268 269 /** 270 * Structure associated with each descriptor of the TX ring of a TX queue. 271 */ 272 struct txgbe_tx_entry_v { 273 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */ 274 }; 275 276 /** 277 * Structure associated with each RX queue. 278 */ 279 struct txgbe_rx_queue { 280 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ 281 volatile struct txgbe_rx_desc *rx_ring; /**< RX ring virtual address. */ 282 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */ 283 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */ 284 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */ 285 struct txgbe_rx_entry *sw_ring; /**< address of RX software ring. */ 286 /**< address of scattered Rx software ring. */ 287 struct txgbe_scattered_rx_entry *sw_sc_ring; 288 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */ 289 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */ 290 uint16_t nb_rx_desc; /**< number of RX descriptors. */ 291 uint16_t rx_tail; /**< current value of RDT register. */ 292 uint16_t nb_rx_hold; /**< number of held free RX desc. */ 293 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */ 294 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */ 295 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */ 296 uint16_t rx_free_thresh; /**< max free RX desc to hold. */ 297 uint16_t queue_id; /**< RX queue index. */ 298 uint16_t reg_idx; /**< RX queue register index. */ 299 /**< Packet type mask for different NICs. */ 300 uint16_t pkt_type_mask; 301 uint16_t port_id; /**< Device port identifier. */ 302 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */ 303 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */ 304 uint8_t rx_deferred_start; /**< not in global dev start. */ 305 /** flags to set in mbuf when a vlan is detected. */ 306 uint64_t vlan_flags; 307 uint64_t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */ 308 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */ 309 struct rte_mbuf fake_mbuf; 310 /** hold packets to return to application */ 311 struct rte_mbuf *rx_stage[RTE_PMD_TXGBE_RX_MAX_BURST * 2]; 312 }; 313 314 /** 315 * TXGBE CTX Constants 316 */ 317 enum txgbe_ctx_num { 318 TXGBE_CTX_0 = 0, /**< CTX0 */ 319 TXGBE_CTX_1 = 1, /**< CTX1 */ 320 TXGBE_CTX_NUM = 2, /**< CTX NUMBER */ 321 }; 322 323 /** Offload features */ 324 union txgbe_tx_offload { 325 uint64_t data[2]; 326 struct { 327 uint64_t ptid:8; /**< Packet Type Identifier. */ 328 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ 329 uint64_t l3_len:9; /**< L3 (IP) Header Length. */ 330 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ 331 uint64_t tso_segsz:16; /**< TCP TSO segment size */ 332 uint64_t vlan_tci:16; 333 /**< VLAN Tag Control Identifier (CPU order). */ 334 335 /* fields for TX offloading of tunnels */ 336 uint64_t outer_tun_len:8; /**< Outer TUN (Tunnel) Hdr Length. */ 337 uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */ 338 uint64_t outer_l3_len:16; /**< Outer L3 (IP) Hdr Length. */ 339 }; 340 }; 341 342 /** 343 * Structure to check if new context need be built 344 */ 345 struct txgbe_ctx_info { 346 uint64_t flags; /**< ol_flags for context build. */ 347 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */ 348 union txgbe_tx_offload tx_offload; 349 /** compare mask for tx offload. */ 350 union txgbe_tx_offload tx_offload_mask; 351 }; 352 353 /** 354 * Structure associated with each TX queue. 355 */ 356 struct txgbe_tx_queue { 357 /** TX ring virtual address. */ 358 volatile struct txgbe_tx_desc *tx_ring; 359 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ 360 union { 361 /**< address of SW ring for scalar PMD. */ 362 struct txgbe_tx_entry *sw_ring; 363 /**< address of SW ring for vector PMD */ 364 struct txgbe_tx_entry_v *sw_ring_v; 365 }; 366 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ 367 volatile uint32_t *tdc_reg_addr; /**< Address of TDC register. */ 368 uint16_t nb_tx_desc; /**< number of TX descriptors. */ 369 uint16_t tx_tail; /**< current value of TDT reg. */ 370 /**< Start freeing TX buffers if there are less free descriptors than 371 * this value. 372 */ 373 uint16_t tx_free_thresh; 374 /** Index to last TX descriptor to have been cleaned. */ 375 uint16_t last_desc_cleaned; 376 /** Total number of TX descriptors ready to be allocated. */ 377 uint16_t nb_tx_free; 378 uint16_t tx_next_dd; /**< next desc to scan for DD bit */ 379 uint16_t queue_id; /**< TX queue index. */ 380 uint16_t reg_idx; /**< TX queue register index. */ 381 uint16_t port_id; /**< Device port identifier. */ 382 uint8_t pthresh; /**< Prefetch threshold register. */ 383 uint8_t hthresh; /**< Host threshold register. */ 384 uint8_t wthresh; /**< Write-back threshold reg. */ 385 uint64_t offloads; /* Tx offload flags of DEV_TX_OFFLOAD_* */ 386 uint32_t ctx_curr; /**< Hardware context states. */ 387 /** Hardware context0 history. */ 388 struct txgbe_ctx_info ctx_cache[TXGBE_CTX_NUM]; 389 const struct txgbe_txq_ops *ops; /**< txq ops */ 390 uint8_t tx_deferred_start; /**< not in global dev start. */ 391 }; 392 393 struct txgbe_txq_ops { 394 void (*release_mbufs)(struct txgbe_tx_queue *txq); 395 void (*free_swring)(struct txgbe_tx_queue *txq); 396 void (*reset)(struct txgbe_tx_queue *txq); 397 }; 398 399 /* Takes an ethdev and a queue and sets up the tx function to be used based on 400 * the queue parameters. Used in tx_queue_setup by primary process and then 401 * in dev_init by secondary process when attaching to an existing ethdev. 402 */ 403 void txgbe_set_tx_function(struct rte_eth_dev *dev, struct txgbe_tx_queue *txq); 404 405 void txgbe_set_rx_function(struct rte_eth_dev *dev); 406 int txgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt); 407 408 uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev); 409 uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev); 410 uint64_t txgbe_get_rx_port_offloads(struct rte_eth_dev *dev); 411 uint64_t txgbe_get_tx_queue_offloads(struct rte_eth_dev *dev); 412 413 #endif /* _TXGBE_RXTX_H_ */ 414