1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Inc. ([email protected]). All rights
3 * reserved.
4 *
5 *
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11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
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27
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38 ***********************license end**************************************/
39
40
41
42
43
44
45
46 /**
47 * @file
48 *
49 * Interface to the TWSI / I2C bus
50 *
51 * <hr>$Revision: 70030 $<hr>
52 *
53 */
54 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55 #include <linux/i2c.h>
56
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-twsi.h>
59 #else
60 #include "cvmx.h"
61 #include "cvmx-twsi.h"
62 #if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
63 #include "cvmx-csr-db.h"
64 #endif
65 #endif
66
67 //#define PRINT_TWSI_CONFIG
68 #ifdef PRINT_TWSI_CONFIG
69 #define twsi_printf printf
70 #else
71 #define twsi_printf(...)
72 #define cvmx_csr_db_decode(...)
73 #endif
74
75 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
76 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
__cvmx_twsix_get_adapter(int twsi_id)77 static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
78 {
79 struct octeon_i2c {
80 wait_queue_head_t queue;
81 struct i2c_adapter adap;
82 int irq;
83 int twsi_freq;
84 int sys_freq;
85 resource_size_t twsi_phys;
86 void __iomem *twsi_base;
87 resource_size_t regsize;
88 device_t dev;
89 int broken_irq_mode;
90 };
91 struct i2c_adapter *adapter;
92 struct octeon_i2c *i2c;
93
94 adapter = i2c_get_adapter(0);
95 if (adapter == NULL)
96 return NULL;
97 i2c = container_of(adapter, struct octeon_i2c, adap);
98 return &i2c[twsi_id].adap;
99 }
100 #endif
101 #endif
102
103
104 /**
105 * Do a twsi read from a 7 bit device address using an (optional) internal address.
106 * Up to 8 bytes can be read at a time.
107 *
108 * @param twsi_id which Octeon TWSI bus to use
109 * @param dev_addr Device address (7 bit)
110 * @param internal_addr
111 * Internal address. Can be 0, 1 or 2 bytes in width
112 * @param num_bytes Number of data bytes to read
113 * @param ia_width_bytes
114 * Internal address size in bytes (0, 1, or 2)
115 * @param data Pointer argument where the read data is returned.
116 *
117 * @return read data returned in 'data' argument
118 * Number of bytes read on success
119 * -1 on failure
120 */
cvmx_twsix_read_ia(int twsi_id,uint8_t dev_addr,uint16_t internal_addr,int num_bytes,int ia_width_bytes,uint64_t * data)121 int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data)
122 {
123 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
124 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
125 struct i2c_adapter *adapter;
126 u8 data_buf[8];
127 u8 addr_buf[8];
128 struct i2c_msg msg[2];
129 uint64_t r;
130 int i, j;
131
132 if (ia_width_bytes == 0)
133 return cvmx_twsix_read(twsi_id, dev_addr, num_bytes, data);
134
135 BUG_ON(ia_width_bytes > 2);
136 BUG_ON(num_bytes > 8 || num_bytes < 1);
137
138 adapter = __cvmx_twsix_get_adapter(twsi_id);
139 if (adapter == NULL)
140 return -1;
141
142 for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
143 addr_buf[j] = (u8)(internal_addr >> (i * 8));
144
145 msg[0].addr = dev_addr;
146 msg[0].flags = 0;
147 msg[0].len = ia_width_bytes;
148 msg[0].buf = addr_buf;
149
150 msg[1].addr = dev_addr;
151 msg[1].flags = I2C_M_RD;
152 msg[1].len = num_bytes;
153 msg[1].buf = data_buf;
154
155 i = i2c_transfer(adapter, msg, 2);
156
157 i2c_put_adapter(adapter);
158
159 if (i == 2) {
160 r = 0;
161 for (i = 0; i < num_bytes; i++)
162 r = (r << 8) | data_buf[i];
163 *data = r;
164 return num_bytes;
165 } else {
166 return -1;
167 }
168 # else
169 BUG(); /* The I2C driver is not compiled in */
170 # endif
171 #else
172 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
173 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
174 int retry_limit = 5;
175
176 if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
177 return -1;
178 retry:
179 twsi_ext.u64 = 0;
180 sw_twsi_val.u64 = 0;
181 sw_twsi_val.s.v = 1;
182 sw_twsi_val.s.r = 1;
183 sw_twsi_val.s.sovr = 1;
184 sw_twsi_val.s.size = num_bytes - 1;
185 sw_twsi_val.s.a = dev_addr;
186
187 if (ia_width_bytes > 0) {
188 sw_twsi_val.s.op = 1;
189 sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
190 sw_twsi_val.s.eop_ia = internal_addr & 0x7;
191 }
192 if (ia_width_bytes == 2) {
193 sw_twsi_val.s.eia = 1;
194 twsi_ext.s.ia = internal_addr >> 8;
195 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
196 }
197
198 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
199 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
200 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
201 cvmx_wait(1000);
202 twsi_printf("Results:\n");
203 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
204 if (!sw_twsi_val.s.r)
205 {
206 /* Check the reason for the failure. We may need to retry to handle multi-master
207 ** configurations.
208 ** Lost arbitration : 0x38, 0x68, 0xB0, 0x78
209 ** Core busy as slave: 0x80, 0x88, 0xA0, 0xA8, 0xB8, 0xC0, 0xC8
210 */
211 if (sw_twsi_val.s.d == 0x38
212 || sw_twsi_val.s.d == 0x68
213 || sw_twsi_val.s.d == 0xB0
214 || sw_twsi_val.s.d == 0x78
215 || sw_twsi_val.s.d == 0x80
216 || sw_twsi_val.s.d == 0x88
217 || sw_twsi_val.s.d == 0xA0
218 || sw_twsi_val.s.d == 0xA8
219 || sw_twsi_val.s.d == 0xB8
220 || sw_twsi_val.s.d == 0xC8)
221 {
222 if (retry_limit-- > 0)
223 {
224 cvmx_wait_usec(100);
225 goto retry;
226 }
227 }
228 /* For all other errors, return an error code */
229 return -1;
230 }
231
232 *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
233 if (num_bytes > 4) {
234 twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
235 *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
236 }
237 return num_bytes;
238 #endif
239 }
240
241 /**
242 * Read from a TWSI device (7 bit device address only) without generating any
243 * internal addresses.
244 * Read from 1-8 bytes and returns them in the data pointer.
245 *
246 * @param twsi_id TWSI interface on Octeon to use
247 * @param dev_addr TWSI device address (7 bit only)
248 * @param num_bytes number of bytes to read
249 * @param data Pointer to data read from TWSI device
250 *
251 * @return Number of bytes read on success
252 * -1 on error
253 */
cvmx_twsix_read(int twsi_id,uint8_t dev_addr,int num_bytes,uint64_t * data)254 int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data)
255 {
256 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
257 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
258 struct i2c_adapter *adapter;
259 u8 data_buf[8];
260 struct i2c_msg msg[1];
261 uint64_t r;
262 int i;
263
264 BUG_ON(num_bytes > 8 || num_bytes < 1);
265
266 adapter = __cvmx_twsix_get_adapter(twsi_id);
267 if (adapter == NULL)
268 return -1;
269
270 msg[0].addr = dev_addr;
271 msg[0].flags = I2C_M_RD;
272 msg[0].len = num_bytes;
273 msg[0].buf = data_buf;
274
275 i = i2c_transfer(adapter, msg, 1);
276
277 i2c_put_adapter(adapter);
278
279 if (i == 1) {
280 r = 0;
281 for (i = 0; i < num_bytes; i++)
282 r = (r << 8) | data_buf[i];
283 *data = r;
284 return num_bytes;
285 } else {
286 return -1;
287 }
288 # else
289 BUG(); /* The I2C driver is not compiled in */
290 # endif
291 #else
292 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
293 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
294 int retry_limit = 5;
295
296 if (num_bytes > 8 || num_bytes < 1)
297 return -1;
298 retry:
299 sw_twsi_val.u64 = 0;
300 sw_twsi_val.s.v = 1;
301 sw_twsi_val.s.r = 1;
302 sw_twsi_val.s.a = dev_addr;
303 sw_twsi_val.s.sovr = 1;
304 sw_twsi_val.s.size = num_bytes - 1;
305
306 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
307 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
308 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
309 cvmx_wait(1000);
310 twsi_printf("Results:\n");
311 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
312 if (!sw_twsi_val.s.r)
313 if (!sw_twsi_val.s.r)
314 {
315 /* Check the reason for the failure. We may need to retry to handle multi-master
316 ** configurations.
317 ** Lost arbitration : 0x38, 0x68, 0xB0, 0x78
318 ** Core busy as slave: 0x80, 0x88, 0xA0, 0xA8, 0xB8, 0xC0, 0xC8
319 */
320 if (sw_twsi_val.s.d == 0x38
321 || sw_twsi_val.s.d == 0x68
322 || sw_twsi_val.s.d == 0xB0
323 || sw_twsi_val.s.d == 0x78
324 || sw_twsi_val.s.d == 0x80
325 || sw_twsi_val.s.d == 0x88
326 || sw_twsi_val.s.d == 0xA0
327 || sw_twsi_val.s.d == 0xA8
328 || sw_twsi_val.s.d == 0xB8
329 || sw_twsi_val.s.d == 0xC8)
330 {
331 if (retry_limit-- > 0)
332 {
333 cvmx_wait_usec(100);
334 goto retry;
335 }
336 }
337 /* For all other errors, return an error code */
338 return -1;
339 }
340
341 *data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
342 if (num_bytes > 4) {
343 twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
344 *data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
345 }
346 return num_bytes;
347 #endif
348 }
349
350 /**
351 * Perform a twsi write operation to a 7 bit device address.
352 *
353 * Note that many eeprom devices have page restrictions regarding address boundaries
354 * that can be crossed in one write operation. This is device dependent, and this routine
355 * does nothing in this regard.
356 * This command does not generate any internal addressess.
357 *
358 * @param twsi_id Octeon TWSI interface to use
359 * @param dev_addr TWSI device address
360 * @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
361 * @param data Data to write
362 *
363 * @return 0 on success
364 * -1 on failure
365 */
cvmx_twsix_write(int twsi_id,uint8_t dev_addr,int num_bytes,uint64_t data)366 int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data)
367 {
368 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
369 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
370 struct i2c_adapter *adapter;
371 u8 data_buf[8];
372 struct i2c_msg msg[1];
373 int i, j;
374
375 BUG_ON(num_bytes > 8 || num_bytes < 1);
376
377 adapter = __cvmx_twsix_get_adapter(twsi_id);
378 if (adapter == NULL)
379 return -1;
380
381 for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
382 data_buf[j] = (u8)(data >> (i * 8));
383
384 msg[0].addr = dev_addr;
385 msg[0].flags = 0;
386 msg[0].len = num_bytes;
387 msg[0].buf = data_buf;
388
389 i = i2c_transfer(adapter, msg, 1);
390
391 i2c_put_adapter(adapter);
392
393 if (i == 1)
394 return num_bytes;
395 else
396 return -1;
397 # else
398 BUG(); /* The I2C driver is not compiled in */
399 # endif
400 #else
401 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
402
403 if (num_bytes > 8 || num_bytes < 1)
404 return -1;
405
406 sw_twsi_val.u64 = 0;
407 sw_twsi_val.s.v = 1;
408 sw_twsi_val.s.a = dev_addr;
409 sw_twsi_val.s.d = data & 0xffffffff;
410 sw_twsi_val.s.sovr = 1;
411 sw_twsi_val.s.size = num_bytes - 1;
412 if (num_bytes > 4) {
413 /* Upper four bytes go into a separate register */
414 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
415 twsi_ext.u64 = 0;
416 twsi_ext.s.d = data >> 32;
417 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
418 }
419 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
420 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
421 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
422 ;
423 twsi_printf("Results:\n");
424 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
425 if (!sw_twsi_val.s.r)
426 return -1;
427
428 return 0;
429 #endif
430 }
431
432 /**
433 * Write 1-8 bytes to a TWSI device using an internal address.
434 *
435 * @param twsi_id which TWSI interface on Octeon to use
436 * @param dev_addr TWSI device address (7 bit only)
437 * @param internal_addr
438 * TWSI internal address (0, 8, or 16 bits)
439 * @param num_bytes Number of bytes to write (1-8)
440 * @param ia_width_bytes
441 * internal address width, in bytes (0, 1, 2)
442 * @param data Data to write. Data is written MSB first on the twsi bus, and only the lower
443 * num_bytes bytes of the argument are valid. (If a 2 byte write is done, only
444 * the low 2 bytes of the argument is used.
445 *
446 * @return Number of bytes read on success,
447 * -1 on error
448 */
cvmx_twsix_write_ia(int twsi_id,uint8_t dev_addr,uint16_t internal_addr,int num_bytes,int ia_width_bytes,uint64_t data)449 int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
450 {
451 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
452 # if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
453 struct i2c_adapter *adapter;
454 u8 data_buf[8];
455 u8 addr_buf[8];
456 struct i2c_msg msg[2];
457 int i, j;
458
459 if (ia_width_bytes == 0)
460 return cvmx_twsix_write(twsi_id, dev_addr, num_bytes, data);
461
462 BUG_ON(ia_width_bytes > 2);
463 BUG_ON(num_bytes > 8 || num_bytes < 1);
464
465 adapter = __cvmx_twsix_get_adapter(twsi_id);
466 if (adapter == NULL)
467 return -1;
468
469
470 for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
471 addr_buf[j] = (u8)(internal_addr >> (i * 8));
472
473 for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
474 data_buf[j] = (u8)(data >> (i * 8));
475
476 msg[0].addr = dev_addr;
477 msg[0].flags = 0;
478 msg[0].len = ia_width_bytes;
479 msg[0].buf = addr_buf;
480
481 msg[1].addr = dev_addr;
482 msg[1].flags = 0;
483 msg[1].len = num_bytes;
484 msg[1].buf = data_buf;
485
486 i = i2c_transfer(adapter, msg, 2);
487
488 i2c_put_adapter(adapter);
489
490 if (i == 2) {
491 /* Poll until reads succeed, or polling times out */
492 int to = 100;
493 while (to-- > 0) {
494 uint64_t data;
495 if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
496 break;
497 }
498 }
499
500 if (i == 2)
501 return num_bytes;
502 else
503 return -1;
504 # else
505 BUG(); /* The I2C driver is not compiled in */
506 # endif
507 #else
508 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
509 cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
510 int to;
511
512 if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
513 return -1;
514
515 twsi_ext.u64 = 0;
516
517 sw_twsi_val.u64 = 0;
518 sw_twsi_val.s.v = 1;
519 sw_twsi_val.s.sovr = 1;
520 sw_twsi_val.s.size = num_bytes - 1;
521 sw_twsi_val.s.a = dev_addr;
522 sw_twsi_val.s.d = 0xFFFFFFFF & data;
523
524 if (ia_width_bytes > 0) {
525 sw_twsi_val.s.op = 1;
526 sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
527 sw_twsi_val.s.eop_ia = internal_addr & 0x7;
528 }
529 if (ia_width_bytes == 2) {
530 sw_twsi_val.s.eia = 1;
531 twsi_ext.s.ia = internal_addr >> 8;
532 }
533 if (num_bytes > 4)
534 twsi_ext.s.d = data >> 32;
535
536 twsi_printf("%s: twsi_id=%x, dev_addr=%x, internal_addr=%x\n\tnum_bytes=%d, ia_width_bytes=%d, data=%lx\n",
537 __FUNCTION__, twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
538 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
539 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
540 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
541 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
542 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
543 ;
544 twsi_printf("Results:\n");
545 cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
546
547 /* Poll until reads succeed, or polling times out */
548 to = 100;
549 while (to-- > 0) {
550 uint64_t data;
551 if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
552 break;
553 }
554 if (to <= 0)
555 return -1;
556
557 return num_bytes;
558 #endif
559 }
560