Home
last modified time | relevance | path

Searched refs:transfer (Results 1 – 25 of 127) sorted by relevance

123456

/f-stack/freebsd/contrib/device-tree/Bindings/dma/
H A Dst,stm32-mdma.yaml24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
28 0x2: Destination address pointer is incremented after each data transfer
29 0x3: Destination address pointer is decremented after each data transfer
40 -bit 25-18: The number of bytes to be transferred in a single transfer
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
H A Dmilbeaut-m10v-hdmac.txt3 Milbeaut AHB DMA controller has transfer capability below.
4 - device to memory transfer
5 - memory to device transfer
H A Dfsl-imx-sdma.txt27 The second cell of dma phandle specifies the peripheral type of DMA transfer.
30 ID transfer type
58 The third cell specifies the transfer priority as below.
60 ID transfer priority
H A Dsocionext,uniphier-xdmac.yaml11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
35 2. Transfer request factor number, If no transfer factor, use 0.
H A Dst,stm32-dma.yaml41 0x1: Direct mode: each DMA request immediately initiates a transfer
76 supports memory-to-memory transfer
H A Dmilbeaut-m10v-xdmac.txt3 Milbeaut AXI DMA controller has only memory to memory transfer capability.
/f-stack/freebsd/contrib/device-tree/Bindings/spi/
H A Dspi-xilinx.txt12 - xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified
21 xlnx,num-transfer-bits = <32>;
H A Dspi-pl022.yaml47 description: delay in ms following transfer completion before the
54 priority to minimise the transfer latency on the bus (boolean)
90 description: Specifies the transfer mode
H A Dspi-fsl-dspi.txt30 select and the start of clock signal, at the start of a transfer.
32 signal and deactivating chip select, at the end of a transfer.
/f-stack/freebsd/contrib/device-tree/Bindings/misc/
H A Datmel-ssc.txt5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
31 - PDC transfer:
40 - DMA transfer:
H A Dolpc,xo1.75-ec.txt8 to receive a transfer (that is, when TX FIFO contains the response data) by
/f-stack/freebsd/arm/allwinner/
H A Dsunxi_dma_if.m82 # Start DMA channel transfer
84 METHOD int transfer {
93 # Halt DMA channel transfer
H A Daw_spi.c151 int transfer; member
457 sc->transfer = 0; in aw_spi_intr()
513 sc->transfer = 1; in aw_spi_xfer()
515 while (error == 0 && sc->transfer != 0) in aw_spi_xfer()
/f-stack/dpdk/drivers/net/mlx5/
H A Dmlx5_flow_meter.c59 fm->transfer ? fm->mfts->transfer.tbl->obj : in mlx5_flow_meter_action_create()
631 .transfer = priv->config.dv_esw_en ? 1 : 0, in mlx5_flow_meter_create()
721 .transfer = priv->config.dv_esw_en ? 1 : 0, in mlx5_flow_meter_destroy()
1183 attr->transfer == fm->transfer && in mlx5_flow_meter_attach()
1192 fm->transfer = attr->transfer; in mlx5_flow_meter_attach()
1201 fm->transfer = 0; in mlx5_flow_meter_attach()
1233 fm->transfer = 0; in mlx5_flow_meter_detach()
1263 .transfer = priv->config.dv_esw_en ? 1 : 0, in mlx5_flow_meter_flush()
H A Dmlx5_flow_dv.c1572 if (!attr->transfer) in flow_dv_validate_item_port_id()
3535 if (attr->transfer) in flow_dv_create_action_raw_encap()
3577 if (attr->transfer) in flow_dv_create_action_push_vlan()
3937 .transfer = !!attributes->transfer, in flow_dv_validate_action_jump()
4006 if (!attr->transfer) in flow_dv_validate_action_port_id()
4123 if (fm->ref_cnt && (!(fm->transfer == attr->transfer || in mlx5_flow_validate_action_meter()
5268 .transfer = !!attr->transfer, in flow_dv_validate()
6255 dev_flow->dv.transfer = attr->transfer; in flow_dv_prepare()
9657 .transfer = !!attr->transfer, in flow_dv_translate()
9688 if (attr->transfer) in flow_dv_translate()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/i2c/
H A Dnvidia,tegra20-i2c.txt22 as per I2C core API transfer flags. Driver of I2C controller is
23 compatible with "nvidia,tegra30-i2c" to enable the continue transfer
25 continue transfer support.
32 - Tegra30/Tegra20 I2C controller has enabled per packet transfer by
H A Di2c-st.txt11 operation for I2C transfer.
22 when I2C instance is not performing a transfer.
/f-stack/freebsd/contrib/device-tree/Bindings/mailbox/
H A Dti,secure-proxy.txt20 - #mbox-cells Shall be 1 and shall refer to the transfer path
22 - interrupt-names: Contains interrupt names matching the rx transfer path
H A Dti,message-manager.txt20 order referring to the transfer path.
21 - interrupt-names: Contains interrupt names matching the rx transfer path
/f-stack/freebsd/contrib/device-tree/Bindings/input/rmi4/
H A Drmi_spi.txt21 - spi-rx-delay-us: microsecond delay after a read transfer.
22 - spi-tx-delay-us: microsecond delay after a write transfer.
/f-stack/freebsd/contrib/device-tree/Bindings/display/msm/
H A Ddsi.txt125 - qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
127 the clock rate according to the expected transfer time.
135 transfer time that could be achieved.
189 qcom,mdss-mdp-transfer-time-us = <12000>;
/f-stack/app/redis-5.0.5/
H A D.gitignore19 src/transfer.sh
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dsprd-mcdt.txt3 The Multi-channel data transfer controller is used for sound stream
/f-stack/dpdk/app/test-flow-perf/
H A Dflow_gen.c32 attr->transfer = 1; in fill_attributes()
/f-stack/freebsd/contrib/device-tree/Bindings/crypto/
H A Dqcom-qce.txt9 "bus" clocks data transfer interface

123456