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/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dsdhci-sprd.txt33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
H A Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
42 Notes for the sdr-timing and ddr-timing values:
48 Valid values for SDR and DDR CIU clock timing for Exynos5250:
87 samsung,dw-mshc-sdr-timing = <2 3>;
88 samsung,dw-mshc-ddr-timing = <1 2>;
89 samsung,dw-mshc-hs400-timing = <0 2>;
H A Dcdns,sdhci.yaml38 description: Value of the delay in the input path for SD high-speed timing
44 description: Value of the delay in the input path for legacy timing
50 description: Value of the delay in the input path for SD UHS SDR12 timing
56 description: Value of the delay in the input path for SD UHS SDR25 timing
62 description: Value of the delay in the input path for SD UHS SDR50 timing
68 description: Value of the delay in the input path for SD UHS DDR50 timing
74 description: Value of the delay in the input path for MMC high-speed timing
80 description: Value of the delay in the input path for eMMC high-speed DDR timing
/f-stack/freebsd/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt29 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set
32 Each "emc-timings" node should contain a "timing" subnode for every supported
35 Required properties for "timing" nodes :
36 - clock-frequency : Should contain the memory clock rate to which this timing
39 parent of the EMC clock should be running at this timing.
44 timing.
93 timing-12750000 {
99 timing-20400000 {
/f-stack/freebsd/contrib/device-tree/Bindings/ata/
H A Dahci-ceva.txt8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
25 - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
33 - ceva,p1-retry-params: Retry interval timing value for port 1.
/f-stack/freebsd/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,v-tc.txt4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
H A Dxlnx,v-tpg.txt29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/f-stack/freebsd/contrib/device-tree/Bindings/display/panel/
H A Ddisplay-timings.yaml18 and to specify the timing that is native for the display.
27 The default display timing is the one specified as native-mode.
32 "^timing":
35 - $ref: panel-timing.yaml#
43 * Example that specifies panel timing using minimum, typical,
H A Dpanel-timing.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
7 title: panel timing bindings
14 There are different ways of describing the timing data of a panel. The
46 This matches the timing diagrams often found in data sheets.
73 description: Horizontal front porch panel timing
86 description: Horizontal back porch timing
99 description: Horizontal sync length panel timing
112 description: Vertical front porch panel timing
125 description: Vertical back porch panel timing
138 description: Vertical sync length panel timing
H A Dpanel-dpi.yaml28 panel-timing: true
35 - panel-timing
53 panel-timing {
H A Dadvantech,idk-2121wr.yaml37 panel-timing: true
75 - panel-timing
88 panel-timing {
H A Dsgd,gktw70sdae4se.yaml31 panel-timing: true
49 panel-timing {
H A Dadvantech,idk-1110wr.yaml31 panel-timing: true
49 panel-timing {
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dexynos5410-smdk5410.dts45 samsung,dw-mshc-sdr-timing = <2 3>;
46 samsung,dw-mshc-ddr-timing = <1 2>;
55 samsung,dw-mshc-sdr-timing = <2 3>;
56 samsung,dw-mshc-ddr-timing = <1 2>;
97 samsung,srom-timing = <9 12 1 9 1 1>;
H A Dtegra124-nyan-blaze-emc.dtsi7 timing-12750000 {
13 timing-20400000 {
19 timing-40800000 {
25 timing-68000000 {
31 timing-102000000 {
37 timing-204000000 {
43 timing-300000000 {
49 timing-396000000 {
56 timing-600000000 {
62 timing-792000000 {
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi7 timing-12750000 {
13 timing-20400000 {
19 timing-40800000 {
25 timing-68000000 {
31 timing-102000000 {
37 timing-204000000 {
43 timing-300000000 {
49 timing-396000000 {
55 timing-528000000 {
61 timing-600000000 {
[all …]
H A Dtegra124-apalis-emc.dtsi12 timing-12750000 {
18 timing-20400000 {
24 timing-40800000 {
30 timing-68000000 {
36 timing-102000000 {
42 timing-204000000 {
48 timing-300000000 {
54 timing-396000000 {
60 timing-528000000 {
66 timing-600000000 {
[all …]
H A Dexynos5260-xyref5260.dts72 samsung,dw-mshc-sdr-timing = <0 4>;
73 samsung,dw-mshc-ddr-timing = <0 2>;
84 samsung,dw-mshc-sdr-timing = <2 3>;
85 samsung,dw-mshc-ddr-timing = <1 2>;
H A Dimx27-eukrea-cpuimx27.dtsi100 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
108 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
121 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
134 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
147 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi8 timing-25500000 {
33 timing-51000000 {
58 timing-102000000 {
83 timing-204000000 {
108 timing-333500000 {
133 timing-667000000 {
162 timing-25500000 {
187 timing-51000000 {
212 timing-102000000 {
318 timing-25500000 {
[all …]
H A Dexynos3250-artik5-eval.dts29 samsung,dw-mshc-sdr-timing = <0 1>;
30 samsung,dw-mshc-ddr-timing = <1 2>;
H A Dtegra124-nyan-big-emc.dtsi11 timing-12750000 {
17 timing-20400000 {
23 timing-40800000 {
29 timing-68000000 {
35 timing-102000000 {
41 timing-204000000 {
47 timing-300000000 {
53 timing-396000000 {
82 timing-12750000 {
88 timing-20400000 {
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/bus/
H A Dimx-weim.txt53 - fsl,weim-cs-timing: The timing array, contains timing values for the
83 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
90 In this case, both chip select 0 and 1 will be configured with the same timing
109 fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
/f-stack/freebsd/contrib/device-tree/Bindings/display/exynos/
H A Dexynos7-decon.txt30 - i80-if-timings: timing configuration for lcd i80 interface support.
34 - display-timings: timing settings for DECON, as described in document [1].
38 [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt

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