1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2018 Intel Corporation 3 */ 4 5 #ifndef _IFPGA_DEFINES_H_ 6 #define _IFPGA_DEFINES_H_ 7 8 #include "ifpga_compat.h" 9 10 #define MAX_FPGA_PORT_NUM 4 11 12 #define FME_FEATURE_HEADER "fme_hdr" 13 #define FME_FEATURE_THERMAL_MGMT "fme_thermal" 14 #define FME_FEATURE_POWER_MGMT "fme_power" 15 #define FME_FEATURE_GLOBAL_IPERF "fme_iperf" 16 #define FME_FEATURE_GLOBAL_ERR "fme_error" 17 #define FME_FEATURE_PR_MGMT "fme_pr" 18 #define FME_FEATURE_EMIF_MGMT "fme_emif" 19 #define FME_FEATURE_HSSI_ETH "fme_hssi" 20 #define FME_FEATURE_GLOBAL_DPERF "fme_dperf" 21 #define FME_FEATURE_QSPI_FLASH "fme_qspi_flash" 22 #define FME_FEATURE_MAX10_SPI "fme_max10_spi" 23 #define FME_FEATURE_NIOS_SPI "fme_nios_spi" 24 #define FME_FEATURE_I2C_MASTER "fme_i2c_master" 25 #define FME_FEATURE_ETH_GROUP "fme_eth_group" 26 27 #define PORT_FEATURE_HEADER "port_hdr" 28 #define PORT_FEATURE_UAFU "port_uafu" 29 #define PORT_FEATURE_ERR "port_err" 30 #define PORT_FEATURE_UMSG "port_umsg" 31 #define PORT_FEATURE_PR "port_pr" 32 #define PORT_FEATURE_UINT "port_uint" 33 #define PORT_FEATURE_STP "port_stp" 34 35 /* 36 * do not check the revision id as id may be dynamic under 37 * some cases, e.g, UAFU. 38 */ 39 #define SKIP_REVISION_CHECK 0xff 40 41 #define FME_HEADER_REVISION 1 42 #define FME_THERMAL_MGMT_REVISION 0 43 #define FME_POWER_MGMT_REVISION 1 44 #define FME_GLOBAL_IPERF_REVISION 1 45 #define FME_GLOBAL_ERR_REVISION 1 46 #define FME_PR_MGMT_REVISION 2 47 #define FME_HSSI_ETH_REVISION 0 48 #define FME_GLOBAL_DPERF_REVISION 0 49 #define FME_QSPI_REVISION 0 50 #define FME_MAX10_SPI 0 51 #define FME_I2C_MASTER 0 52 53 #define PORT_HEADER_REVISION 0 54 /* UAFU's header info depends on the downloaded GBS */ 55 #define PORT_UAFU_REVISION SKIP_REVISION_CHECK 56 #define PORT_ERR_REVISION 1 57 #define PORT_UMSG_REVISION 0 58 #define PORT_UINT_REVISION 0 59 #define PORT_STP_REVISION 1 60 61 #define FEATURE_TYPE_AFU 0x1 62 #define FEATURE_TYPE_BBB 0x2 63 #define FEATURE_TYPE_PRIVATE 0x3 64 #define FEATURE_TYPE_FIU 0x4 65 66 #define FEATURE_FIU_ID_FME 0x0 67 #define FEATURE_FIU_ID_PORT 0x1 68 69 /* Reserved 0xfe for Header, 0xff for AFU*/ 70 #define FEATURE_ID_FIU_HEADER 0xfe 71 #define FEATURE_ID_AFU 0xff 72 73 enum fpga_id_type { 74 FME_ID, 75 PORT_ID, 76 FPGA_ID_MAX, 77 }; 78 79 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 80 #define FME_FEATURE_ID_THERMAL_MGMT 0x1 81 #define FME_FEATURE_ID_POWER_MGMT 0x2 82 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3 83 #define FME_FEATURE_ID_GLOBAL_ERR 0x4 84 #define FME_FEATURE_ID_PR_MGMT 0x5 85 #define FME_FEATURE_ID_HSSI_ETH 0x6 86 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7 87 #define FME_FEATURE_ID_QSPI_FLASH 0x8 88 #define FME_FEATURE_ID_EMIF_MGMT 0x9 89 #define FME_FEATURE_ID_MAX10_SPI 0xe 90 #define FME_FEATURE_ID_NIOS_SPI 0xd 91 #define FME_FEATURE_ID_I2C_MASTER 0xf 92 #define FME_FEATURE_ID_ETH_GROUP 0x10 93 94 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 95 #define PORT_FEATURE_ID_ERROR 0x10 96 #define PORT_FEATURE_ID_UMSG 0x12 97 #define PORT_FEATURE_ID_UINT 0x13 98 #define PORT_FEATURE_ID_STP 0x14 99 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU 100 101 /* 102 * All headers and structures must be byte-packed to match the spec. 103 */ 104 #pragma pack(push, 1) 105 106 struct feature_header { 107 union { 108 u64 csr; 109 struct { 110 u16 id:12; 111 u8 revision:4; 112 u32 next_header_offset:24; 113 u8 end_of_list:1; 114 u32 reserved:19; 115 u8 type:4; 116 }; 117 }; 118 }; 119 120 struct feature_bbb_header { 121 struct uuid guid; 122 }; 123 124 struct feature_afu_header { 125 struct uuid guid; 126 union { 127 u64 csr; 128 struct { 129 u64 next_afu:24; 130 u64 reserved:40; 131 }; 132 }; 133 }; 134 135 struct feature_fiu_header { 136 struct uuid guid; 137 union { 138 u64 csr; 139 struct { 140 u64 next_afu:24; 141 u64 reserved:40; 142 }; 143 }; 144 }; 145 146 struct feature_fme_capability { 147 union { 148 u64 csr; 149 struct { 150 u8 fabric_verid; /* Fabric version ID */ 151 u8 socket_id:1; /* Socket id */ 152 u8 rsvd1:3; /* Reserved */ 153 /* pci0 link available yes /no */ 154 u8 pci0_link_avile:1; 155 /* pci1 link available yes /no */ 156 u8 pci1_link_avile:1; 157 /* Coherent (QPI/UPI) link available yes /no */ 158 u8 qpi_link_avile:1; 159 u8 rsvd2:1; /* Reserved */ 160 /* IOMMU or VT-d supported yes/no */ 161 u8 iommu_support:1; 162 u8 num_ports:3; /* Number of ports */ 163 u8 sf_fab_ctl:1; /* Internal validation bit */ 164 u8 rsvd3:3; /* Reserved */ 165 /* 166 * Address width supported in bits 167 * BXT -0x26 , SKX -0x30 168 */ 169 u8 address_width_bits:6; 170 u8 rsvd4:2; /* Reserved */ 171 /* Size of cache supported in kb */ 172 u16 cache_size:12; 173 u8 cache_assoc:4; /* Cache Associativity */ 174 u16 rsvd5:15; /* Reserved */ 175 u8 lock_bit:1; /* Lock bit */ 176 }; 177 }; 178 }; 179 180 #define FME_AFU_ACCESS_PF 0 181 #define FME_AFU_ACCESS_VF 1 182 183 struct feature_fme_port { 184 union { 185 u64 csr; 186 struct { 187 u32 port_offset:24; 188 u8 reserved1; 189 u8 port_bar:3; 190 u32 reserved2:20; 191 u8 afu_access_control:1; 192 u8 reserved3:4; 193 u8 port_implemented:1; 194 u8 reserved4:3; 195 }; 196 }; 197 }; 198 199 struct feature_fme_fab_status { 200 union { 201 u64 csr; 202 struct { 203 u8 upilink_status:4; /* UPI Link Status */ 204 u8 rsvd1:4; /* Reserved */ 205 u8 pci0link_status:1; /* pci0 link status */ 206 u8 rsvd2:3; /* Reserved */ 207 u8 pci1link_status:1; /* pci1 link status */ 208 u64 rsvd3:51; /* Reserved */ 209 }; 210 }; 211 }; 212 213 struct feature_fme_genprotrange2_base { 214 union { 215 u64 csr; 216 struct { 217 u16 rsvd1; /* Reserved */ 218 /* Base Address of memory range */ 219 u8 protected_base_addrss:4; 220 u64 rsvd2:44; /* Reserved */ 221 }; 222 }; 223 }; 224 225 struct feature_fme_genprotrange2_limit { 226 union { 227 u64 csr; 228 struct { 229 u16 rsvd1; /* Reserved */ 230 /* Limit Address of memory range */ 231 u8 protected_limit_addrss:4; 232 u16 rsvd2:11; /* Reserved */ 233 u8 enable:1; /* Enable GENPROTRANGE check */ 234 u32 rsvd3; /* Reserved */ 235 }; 236 }; 237 }; 238 239 struct feature_fme_dxe_lock { 240 union { 241 u64 csr; 242 struct { 243 /* 244 * Determines write access to the DXE region CSRs 245 * 1 - CSR region is locked; 246 * 0 - it is open for write access. 247 */ 248 u8 dxe_early_lock:1; 249 /* 250 * Determines write access to the HSSI CSR 251 * 1 - CSR region is locked; 252 * 0 - it is open for write access. 253 */ 254 u8 dxe_late_lock:1; 255 u64 rsvd:62; 256 }; 257 }; 258 }; 259 260 #define HSSI_ID_NO_HASSI 0 261 #define HSSI_ID_PCIE_RP 1 262 #define HSSI_ID_ETHERNET 2 263 264 struct feature_fme_bitstream_id { 265 union { 266 u64 csr; 267 struct { 268 u32 gitrepo_hash:32; /* GIT repository hash */ 269 /* 270 * HSSI configuration identifier: 271 * 0 - No HSSI 272 * 1 - PCIe-RP 273 * 2 - Ethernet 274 */ 275 u8 hssi_id:4; 276 u16 rsvd1:12; /* Reserved */ 277 /* Bitstream version patch number */ 278 u8 bs_verpatch:4; 279 /* Bitstream version minor number */ 280 u8 bs_verminor:4; 281 /* Bitstream version major number */ 282 u8 bs_vermajor:4; 283 /* Bitstream version debug number */ 284 u8 bs_verdebug:4; 285 }; 286 }; 287 }; 288 289 struct feature_fme_bitstream_md { 290 union { 291 u64 csr; 292 struct { 293 /* Seed number userd for synthesis flow */ 294 u8 synth_seed:4; 295 /* Synthesis date(day number - 2 digits) */ 296 u8 synth_day:8; 297 /* Synthesis date(month number - 2 digits) */ 298 u8 synth_month:8; 299 /* Synthesis date(year number - 2 digits) */ 300 u8 synth_year:8; 301 u64 rsvd:36; /* Reserved */ 302 }; 303 }; 304 }; 305 306 struct feature_fme_iommu_ctrl { 307 union { 308 u64 csr; 309 struct { 310 /* Disables IOMMU prefetcher for C0 channel */ 311 u8 prefetch_disableC0:1; 312 /* Disables IOMMU prefetcher for C1 channel */ 313 u8 prefetch_disableC1:1; 314 /* Disables IOMMU partial cache line writes */ 315 u8 prefetch_wrdisable:1; 316 u8 rsvd1:1; /* Reserved */ 317 /* 318 * Select counter and read value from register 319 * iommu_stat.dbg_counters 320 * 0 - Number of 4K page translation response 321 * 1 - Number of 2M page translation response 322 * 2 - Number of 1G page translation response 323 */ 324 u8 counter_sel:2; 325 u32 rsvd2:26; /* Reserved */ 326 /* Connected to IOMMU SIP Capabilities */ 327 u32 capecap_defeature; 328 }; 329 }; 330 }; 331 332 struct feature_fme_iommu_stat { 333 union { 334 u64 csr; 335 struct { 336 /* Translation Enable bit from IOMMU SIP */ 337 u8 translation_enable:1; 338 /* Drain request in progress */ 339 u8 drain_req_inprog:1; 340 /* Invalidation current state */ 341 u8 inv_state:3; 342 /* C0 Response Buffer current state */ 343 u8 respbuffer_stateC0:3; 344 /* C1 Response Buffer current state */ 345 u8 respbuffer_stateC1:3; 346 /* Last request ID to IOMMU SIP */ 347 u8 last_reqID:4; 348 /* Last IOMMU SIP response ID value */ 349 u8 last_respID:4; 350 /* Last IOMMU SIP response status value */ 351 u8 last_respstatus:3; 352 /* C0 Transaction Buffer is not empty */ 353 u8 transbuf_notEmptyC0:1; 354 /* C1 Transaction Buffer is not empty */ 355 u8 transbuf_notEmptyC1:1; 356 /* C0 Request FIFO is not empty */ 357 u8 reqFIFO_notemptyC0:1; 358 /* C1 Request FIFO is not empty */ 359 u8 reqFIFO_notemptyC1:1; 360 /* C0 Response FIFO is not empty */ 361 u8 respFIFO_notemptyC0:1; 362 /* C1 Response FIFO is not empty */ 363 u8 respFIFO_notemptyC1:1; 364 /* C0 Response FIFO overflow detected */ 365 u8 respFIFO_overflowC0:1; 366 /* C1 Response FIFO overflow detected */ 367 u8 respFIFO_overflowC1:1; 368 /* C0 Transaction Buffer overflow detected */ 369 u8 tranbuf_overflowC0:1; 370 /* C1 Transaction Buffer overflow detected */ 371 u8 tranbuf_overflowC1:1; 372 /* Request FIFO overflow detected */ 373 u8 reqFIFO_overflow:1; 374 /* IOMMU memory read in progress */ 375 u8 memrd_inprog:1; 376 /* IOMMU memory write in progress */ 377 u8 memwr_inprog:1; 378 u8 rsvd1:1; /* Reserved */ 379 /* Value of counter selected by iommu_ctl.counter_sel */ 380 u16 dbg_counters:16; 381 u16 rsvd2:12; /* Reserved */ 382 }; 383 }; 384 }; 385 386 struct feature_fme_pcie0_ctrl { 387 union { 388 u64 csr; 389 struct { 390 u64 vtd_bar_lock:1; /* Lock VT-D BAR register */ 391 u64 rsvd1:3; 392 u64 rciep:1; /* Configure PCIE0 as RCiEP */ 393 u64 rsvd2:59; 394 }; 395 }; 396 }; 397 398 struct feature_fme_llpr_smrr_base { 399 union { 400 u64 csr; 401 struct { 402 u64 rsvd1:12; 403 u64 base:20; /* SMRR2 memory range base address */ 404 u64 rsvd2:32; 405 }; 406 }; 407 }; 408 409 struct feature_fme_llpr_smrr_mask { 410 union { 411 u64 csr; 412 struct { 413 u64 rsvd1:11; 414 u64 valid:1; /* LLPR_SMRR rule is valid or not */ 415 /* 416 * SMRR memory range mask which determines the range 417 * of region being mapped 418 */ 419 u64 phys_mask:20; 420 u64 rsvd2:32; 421 }; 422 }; 423 }; 424 425 struct feature_fme_llpr_smrr2_base { 426 union { 427 u64 csr; 428 struct { 429 u64 rsvd1:12; 430 u64 base:20; /* SMRR2 memory range base address */ 431 u64 rsvd2:32; 432 }; 433 }; 434 }; 435 436 struct feature_fme_llpr_smrr2_mask { 437 union { 438 u64 csr; 439 struct { 440 u64 rsvd1:11; 441 u64 valid:1; /* LLPR_SMRR2 rule is valid or not */ 442 /* 443 * SMRR2 memory range mask which determines the range 444 * of region being mapped 445 */ 446 u64 phys_mask:20; 447 u64 rsvd2:32; 448 }; 449 }; 450 }; 451 452 struct feature_fme_llpr_meseg_base { 453 union { 454 u64 csr; 455 struct { 456 /* A[45:19] of base address memory range */ 457 u64 me_base:27; 458 u64 rsvd:37; 459 }; 460 }; 461 }; 462 463 struct feature_fme_llpr_meseg_limit { 464 union { 465 u64 csr; 466 struct { 467 /* A[45:19] of limit address memory range */ 468 u64 me_limit:27; 469 u64 rsvd1:4; 470 u64 enable:1; /* Enable LLPR MESEG rule */ 471 u64 rsvd2:32; 472 }; 473 }; 474 }; 475 476 struct feature_fme_header { 477 struct feature_header header; 478 struct feature_afu_header afu_header; 479 u64 reserved; 480 u64 scratchpad; 481 struct feature_fme_capability capability; 482 struct feature_fme_port port[MAX_FPGA_PORT_NUM]; 483 struct feature_fme_fab_status fab_status; 484 struct feature_fme_bitstream_id bitstream_id; 485 struct feature_fme_bitstream_md bitstream_md; 486 struct feature_fme_genprotrange2_base genprotrange2_base; 487 struct feature_fme_genprotrange2_limit genprotrange2_limit; 488 struct feature_fme_dxe_lock dxe_lock; 489 struct feature_fme_iommu_ctrl iommu_ctrl; 490 struct feature_fme_iommu_stat iommu_stat; 491 struct feature_fme_pcie0_ctrl pcie0_control; 492 struct feature_fme_llpr_smrr_base smrr_base; 493 struct feature_fme_llpr_smrr_mask smrr_mask; 494 struct feature_fme_llpr_smrr2_base smrr2_base; 495 struct feature_fme_llpr_smrr2_mask smrr2_mask; 496 struct feature_fme_llpr_meseg_base meseg_base; 497 struct feature_fme_llpr_meseg_limit meseg_limit; 498 }; 499 500 struct feature_port_capability { 501 union { 502 u64 csr; 503 struct { 504 u8 port_number:2; /* Port Number 0-3 */ 505 u8 rsvd1:6; /* Reserved */ 506 u16 mmio_size; /* User MMIO size in KB */ 507 u8 rsvd2; /* Reserved */ 508 u8 sp_intr_num:4; /* Supported interrupts num */ 509 u32 rsvd3:28; /* Reserved */ 510 }; 511 }; 512 }; 513 514 struct feature_port_control { 515 union { 516 u64 csr; 517 struct { 518 u8 port_sftrst:1; /* Port Soft Reset */ 519 u8 rsvd1:1; /* Reserved */ 520 u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */ 521 u8 rsvd2:1; /* Reserved */ 522 u8 port_sftrst_ack:1; /* HW ACK for Soft Reset */ 523 u64 rsvd3:59; /* Reserved */ 524 }; 525 }; 526 }; 527 528 #define PORT_POWER_STATE_NORMAL 0 529 #define PORT_POWER_STATE_AP1 1 530 #define PORT_POWER_STATE_AP2 2 531 #define PORT_POWER_STATE_AP6 6 532 533 struct feature_port_status { 534 union { 535 u64 csr; 536 struct { 537 u8 port_freeze:1; /* '1' - freezed '0' - normal */ 538 u8 rsvd1:7; /* Reserved */ 539 u8 power_state:4; /* Power State */ 540 u8 ap1_event:1; /* AP1 event was detected */ 541 u8 ap2_event:1; /* AP2 event was detected */ 542 u64 rsvd2:50; /* Reserved */ 543 }; 544 }; 545 }; 546 547 /* Port Header Register Set */ 548 struct feature_port_header { 549 struct feature_header header; 550 struct feature_afu_header afu_header; 551 u64 port_mailbox; 552 u64 scratchpad; 553 struct feature_port_capability capability; 554 struct feature_port_control control; 555 struct feature_port_status status; 556 u64 rsvd2; 557 u64 user_clk_freq_cmd0; 558 u64 user_clk_freq_cmd1; 559 u64 user_clk_freq_sts0; 560 u64 user_clk_freq_sts1; 561 }; 562 563 struct feature_fme_tmp_threshold { 564 union { 565 u64 csr; 566 struct { 567 u8 tmp_thshold1:7; /* temperature Threshold 1 */ 568 /* temperature Threshold 1 enable/disable */ 569 u8 tmp_thshold1_enable:1; 570 u8 tmp_thshold2:7; /* temperature Threshold 2 */ 571 /* temperature Threshold 2 enable /disable */ 572 u8 tmp_thshold2_enable:1; 573 u8 pro_hot_setpoint:7; /* Proc Hot set point */ 574 u8 rsvd4:1; /* Reserved */ 575 u8 therm_trip_thshold:7; /* Thermeal Trip Threshold */ 576 u8 rsvd3:1; /* Reserved */ 577 u8 thshold1_status:1; /* Threshold 1 Status */ 578 u8 thshold2_status:1; /* Threshold 2 Status */ 579 u8 rsvd5:1; /* Reserved */ 580 /* Thermeal Trip Threshold status */ 581 u8 therm_trip_thshold_status:1; 582 u8 rsvd6:4; /* Reserved */ 583 /* Validation mode- Force Proc Hot */ 584 u8 valmodeforce:1; 585 /* Validation mode - Therm trip Hot */ 586 u8 valmodetherm:1; 587 u8 rsvd2:2; /* Reserved */ 588 u8 thshold_policy:1; /* threshold policy */ 589 u32 rsvd:19; /* Reserved */ 590 }; 591 }; 592 }; 593 594 /* Temperature Sensor Read values format 1 */ 595 struct feature_fme_temp_rdsensor_fmt1 { 596 union { 597 u64 csr; 598 struct { 599 /* Reads out FPGA temperature in celsius */ 600 u8 fpga_temp:7; 601 u8 rsvd0:1; /* Reserved */ 602 /* Temperature reading sequence number */ 603 u16 tmp_reading_seq_num; 604 /* Temperature reading is valid */ 605 u8 tmp_reading_valid:1; 606 u8 rsvd1:7; /* Reserved */ 607 u16 dbg_mode:10; /* Debug mode */ 608 u32 rsvd2:22; /* Reserved */ 609 }; 610 }; 611 }; 612 613 /* Temperature sensor read values format 2 */ 614 struct feature_fme_temp_rdsensor_fmt2 { 615 u64 rsvd; /* Reserved */ 616 }; 617 618 /* Temperature Threshold Capability Register */ 619 struct feature_fme_tmp_threshold_cap { 620 union { 621 u64 csr; 622 struct { 623 /* Temperature Threshold Unsupported */ 624 u8 tmp_thshold_disabled:1; 625 u64 rsvd:63; /* Reserved */ 626 }; 627 }; 628 }; 629 630 /* FME THERNAL FEATURE */ 631 struct feature_fme_thermal { 632 struct feature_header header; 633 struct feature_fme_tmp_threshold threshold; 634 struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1; 635 struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2; 636 struct feature_fme_tmp_threshold_cap threshold_cap; 637 }; 638 639 /* Power Status register */ 640 struct feature_fme_pm_status { 641 union { 642 u64 csr; 643 struct { 644 /* FPGA Power consumed, The format is to be defined */ 645 u32 pwr_consumed:18; 646 /* FPGA Latency Tolerance Reporting */ 647 u8 fpga_latency_report:1; 648 u64 rsvd:45; /* Reserved */ 649 }; 650 }; 651 }; 652 653 /* AP Thresholds */ 654 struct feature_fme_pm_ap_threshold { 655 union { 656 u64 csr; 657 struct { 658 /* 659 * Number of clocks (5ns period) for assertion 660 * of FME_data 661 */ 662 u8 threshold1:7; 663 u8 rsvd1:1; 664 u8 threshold2:7; 665 u8 rsvd2:1; 666 u8 threshold1_status:1; 667 u8 threshold2_status:1; 668 u64 rsvd3:46; /* Reserved */ 669 }; 670 }; 671 }; 672 673 /* Xeon Power Limit */ 674 struct feature_fme_pm_xeon_limit { 675 union { 676 u64 csr; 677 struct { 678 /* Power limit in Watts in 12.3 format */ 679 u16 pwr_limit:15; 680 /* Indicates that power limit has been written */ 681 u8 enable:1; 682 /* 0 - Turbe range, 1 - Entire range */ 683 u8 clamping:1; 684 /* Time constant in XXYYY format */ 685 u8 time:7; 686 u64 rsvd:40; /* Reserved */ 687 }; 688 }; 689 }; 690 691 /* FPGA Power Limit */ 692 struct feature_fme_pm_fpga_limit { 693 union { 694 u64 csr; 695 struct { 696 /* Power limit in Watts in 12.3 format */ 697 u16 pwr_limit:15; 698 /* Indicates that power limit has been written */ 699 u8 enable:1; 700 /* 0 - Turbe range, 1 - Entire range */ 701 u8 clamping:1; 702 /* Time constant in XXYYY format */ 703 u8 time:7; 704 u64 rsvd:40; /* Reserved */ 705 }; 706 }; 707 }; 708 709 /* FME POWER FEATURE */ 710 struct feature_fme_power { 711 struct feature_header header; 712 struct feature_fme_pm_status status; 713 struct feature_fme_pm_ap_threshold threshold; 714 struct feature_fme_pm_xeon_limit xeon_limit; 715 struct feature_fme_pm_fpga_limit fpga_limit; 716 }; 717 718 #define CACHE_CHANNEL_RD 0 719 #define CACHE_CHANNEL_WR 1 720 721 enum iperf_cache_events { 722 IPERF_CACHE_RD_HIT, 723 IPERF_CACHE_WR_HIT, 724 IPERF_CACHE_RD_MISS, 725 IPERF_CACHE_WR_MISS, 726 IPERF_CACHE_RSVD, /* reserved */ 727 IPERF_CACHE_HOLD_REQ, 728 IPERF_CACHE_DATA_WR_PORT_CONTEN, 729 IPERF_CACHE_TAG_WR_PORT_CONTEN, 730 IPERF_CACHE_TX_REQ_STALL, 731 IPERF_CACHE_RX_REQ_STALL, 732 IPERF_CACHE_EVICTIONS, 733 }; 734 735 /* FPMON Cache Control */ 736 struct feature_fme_ifpmon_ch_ctl { 737 union { 738 u64 csr; 739 struct { 740 u8 reset_counters:1; /* Reset Counters */ 741 u8 rsvd1:7; /* Reserved */ 742 u8 freeze:1; /* Freeze if set to 1 */ 743 u8 rsvd2:7; /* Reserved */ 744 u8 cache_event:4; /* Select the cache event */ 745 u8 cci_chsel:1; /* Select the channel */ 746 u64 rsvd3:43; /* Reserved */ 747 }; 748 }; 749 }; 750 751 /* FPMON Cache Counter */ 752 struct feature_fme_ifpmon_ch_ctr { 753 union { 754 u64 csr; 755 struct { 756 /* Cache Counter for even addresse */ 757 u64 cache_counter:48; 758 u16 rsvd:12; /* Reserved */ 759 /* Cache Event being reported */ 760 u8 event_code:4; 761 }; 762 }; 763 }; 764 765 enum iperf_fab_events { 766 IPERF_FAB_PCIE0_RD, 767 IPERF_FAB_PCIE0_WR, 768 IPERF_FAB_PCIE1_RD, 769 IPERF_FAB_PCIE1_WR, 770 IPERF_FAB_UPI_RD, 771 IPERF_FAB_UPI_WR, 772 IPERF_FAB_MMIO_RD, 773 IPERF_FAB_MMIO_WR, 774 }; 775 776 #define FAB_DISABLE_FILTER 0 777 #define FAB_ENABLE_FILTER 1 778 779 /* FPMON FAB Control */ 780 struct feature_fme_ifpmon_fab_ctl { 781 union { 782 u64 csr; 783 struct { 784 u8 reset_counters:1; /* Reset Counters */ 785 u8 rsvd:7; /* Reserved */ 786 u8 freeze:1; /* Set to 1 frozen counter */ 787 u8 rsvd1:7; /* Reserved */ 788 u8 fab_evtcode:4; /* Fabric Event Code */ 789 u8 port_id:2; /* Port ID */ 790 u8 rsvd2:1; /* Reserved */ 791 u8 port_filter:1; /* Port Filter */ 792 u64 rsvd3:40; /* Reserved */ 793 }; 794 }; 795 }; 796 797 /* FPMON Event Counter */ 798 struct feature_fme_ifpmon_fab_ctr { 799 union { 800 u64 csr; 801 struct { 802 u64 fab_cnt:60; /* Fabric event counter */ 803 /* Fabric event code being reported */ 804 u8 event_code:4; 805 }; 806 }; 807 }; 808 809 /* FPMON Clock Counter */ 810 struct feature_fme_ifpmon_clk_ctr { 811 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */ 812 }; 813 814 enum iperf_vtd_events { 815 IPERF_VTD_AFU_MEM_RD_TRANS, 816 IPERF_VTD_AFU_MEM_WR_TRANS, 817 IPERF_VTD_AFU_DEVTLB_RD_HIT, 818 IPERF_VTD_AFU_DEVTLB_WR_HIT, 819 IPERF_VTD_DEVTLB_4K_FILL, 820 IPERF_VTD_DEVTLB_2M_FILL, 821 IPERF_VTD_DEVTLB_1G_FILL, 822 }; 823 824 /* VT-d control register */ 825 struct feature_fme_ifpmon_vtd_ctl { 826 union { 827 u64 csr; 828 struct { 829 u8 reset_counters:1; /* Reset Counters */ 830 u8 rsvd:7; /* Reserved */ 831 u8 freeze:1; /* Set to 1 frozen counter */ 832 u8 rsvd1:7; /* Reserved */ 833 u8 vtd_evtcode:4; /* VTd and TLB event code */ 834 u64 rsvd2:44; /* Reserved */ 835 }; 836 }; 837 }; 838 839 /* VT-d event counter */ 840 struct feature_fme_ifpmon_vtd_ctr { 841 union { 842 u64 csr; 843 struct { 844 u64 vtd_counter:48; /* VTd event counter */ 845 u16 rsvd:12; /* Reserved */ 846 u8 event_code:4; /* VTd event code */ 847 }; 848 }; 849 }; 850 851 enum iperf_vtd_sip_events { 852 IPERF_VTD_SIP_IOTLB_4K_HIT, 853 IPERF_VTD_SIP_IOTLB_2M_HIT, 854 IPERF_VTD_SIP_IOTLB_1G_HIT, 855 IPERF_VTD_SIP_SLPWC_L3_HIT, 856 IPERF_VTD_SIP_SLPWC_L4_HIT, 857 IPERF_VTD_SIP_RCC_HIT, 858 IPERF_VTD_SIP_IOTLB_4K_MISS, 859 IPERF_VTD_SIP_IOTLB_2M_MISS, 860 IPERF_VTD_SIP_IOTLB_1G_MISS, 861 IPERF_VTD_SIP_SLPWC_L3_MISS, 862 IPERF_VTD_SIP_SLPWC_L4_MISS, 863 IPERF_VTD_SIP_RCC_MISS, 864 }; 865 866 /* VT-d SIP control register */ 867 struct feature_fme_ifpmon_vtd_sip_ctl { 868 union { 869 u64 csr; 870 struct { 871 u8 reset_counters:1; /* Reset Counters */ 872 u8 rsvd:7; /* Reserved */ 873 u8 freeze:1; /* Set to 1 frozen counter */ 874 u8 rsvd1:7; /* Reserved */ 875 u8 vtd_evtcode:4; /* VTd and TLB event code */ 876 u64 rsvd2:44; /* Reserved */ 877 }; 878 }; 879 }; 880 881 /* VT-d SIP event counter */ 882 struct feature_fme_ifpmon_vtd_sip_ctr { 883 union { 884 u64 csr; 885 struct { 886 u64 vtd_counter:48; /* VTd event counter */ 887 u16 rsvd:12; /* Reserved */ 888 u8 event_code:4; /* VTd event code */ 889 }; 890 }; 891 }; 892 893 /* FME IPERF FEATURE */ 894 struct feature_fme_iperf { 895 struct feature_header header; 896 struct feature_fme_ifpmon_ch_ctl ch_ctl; 897 struct feature_fme_ifpmon_ch_ctr ch_ctr0; 898 struct feature_fme_ifpmon_ch_ctr ch_ctr1; 899 struct feature_fme_ifpmon_fab_ctl fab_ctl; 900 struct feature_fme_ifpmon_fab_ctr fab_ctr; 901 struct feature_fme_ifpmon_clk_ctr clk; 902 struct feature_fme_ifpmon_vtd_ctl vtd_ctl; 903 struct feature_fme_ifpmon_vtd_ctr vtd_ctr; 904 struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl; 905 struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr; 906 }; 907 908 enum dperf_fab_events { 909 DPERF_FAB_PCIE0_RD, 910 DPERF_FAB_PCIE0_WR, 911 DPERF_FAB_MMIO_RD = 6, 912 DPERF_FAB_MMIO_WR, 913 }; 914 915 /* FPMON FAB Control */ 916 struct feature_fme_dfpmon_fab_ctl { 917 union { 918 u64 csr; 919 struct { 920 u8 reset_counters:1; /* Reset Counters */ 921 u8 rsvd:7; /* Reserved */ 922 u8 freeze:1; /* Set to 1 frozen counter */ 923 u8 rsvd1:7; /* Reserved */ 924 u8 fab_evtcode:4; /* Fabric Event Code */ 925 u8 port_id:2; /* Port ID */ 926 u8 rsvd2:1; /* Reserved */ 927 u8 port_filter:1; /* Port Filter */ 928 u64 rsvd3:40; /* Reserved */ 929 }; 930 }; 931 }; 932 933 /* FPMON Event Counter */ 934 struct feature_fme_dfpmon_fab_ctr { 935 union { 936 u64 csr; 937 struct { 938 u64 fab_cnt:60; /* Fabric event counter */ 939 /* Fabric event code being reported */ 940 u8 event_code:4; 941 }; 942 }; 943 }; 944 945 /* FPMON Clock Counter */ 946 struct feature_fme_dfpmon_clk_ctr { 947 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */ 948 }; 949 950 /* FME DPERF FEATURE */ 951 struct feature_fme_dperf { 952 struct feature_header header; 953 u64 rsvd[3]; 954 struct feature_fme_dfpmon_fab_ctl fab_ctl; 955 struct feature_fme_dfpmon_fab_ctr fab_ctr; 956 struct feature_fme_dfpmon_clk_ctr clk; 957 }; 958 959 struct feature_fme_error0 { 960 #define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */ 961 union { 962 u64 csr; 963 struct { 964 u8 fabric_err:1; /* Fabric error */ 965 u8 fabfifo_overflow:1; /* Fabric fifo overflow */ 966 u8 reserved2:3; 967 /* AFU PF/VF access mismatch detected */ 968 u8 afu_acc_mode_err:1; 969 u8 reserved6:1; 970 /* PCIE0 CDC Parity Error */ 971 u8 pcie0cdc_parity_err:5; 972 /* PCIE1 CDC Parity Error */ 973 u8 pcie1cdc_parity_err:5; 974 /* CVL CDC Parity Error */ 975 u8 cvlcdc_parity_err:3; 976 u8 fpgaseuerr:1; 977 u64 rsvd:43; /* Reserved */ 978 }; 979 }; 980 }; 981 982 /* PCIe0 Error Status register */ 983 struct feature_fme_pcie0_error { 984 #define FME_PCIE0_ERROR_MASK 0xFFUL 985 union { 986 u64 csr; 987 struct { 988 u8 formattype_err:1; /* TLP format/type error */ 989 u8 MWAddr_err:1; /* TLP MW address error */ 990 u8 MWAddrLength_err:1; /* TLP MW length error */ 991 u8 MRAddr_err:1; /* TLP MR address error */ 992 u8 MRAddrLength_err:1; /* TLP MR length error */ 993 u8 cpl_tag_err:1; /* TLP CPL tag error */ 994 u8 cpl_status_err:1; /* TLP CPL status error */ 995 u8 cpl_timeout_err:1; /* TLP CPL timeout */ 996 u8 cci_parity_err:1; /* CCI bridge parity error */ 997 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */ 998 u64 rsvd:52; /* Reserved */ 999 u8 vfnumb_err:1; /* Number of error VF */ 1000 u8 funct_type_err:1; /* Virtual (1) or Physical */ 1001 }; 1002 }; 1003 }; 1004 1005 /* PCIe1 Error Status register */ 1006 struct feature_fme_pcie1_error { 1007 #define FME_PCIE1_ERROR_MASK 0xFFUL 1008 union { 1009 u64 csr; 1010 struct { 1011 u8 formattype_err:1; /* TLP format/type error */ 1012 u8 MWAddr_err:1; /* TLP MW address error */ 1013 u8 MWAddrLength_err:1; /* TLP MW length error */ 1014 u8 MRAddr_err:1; /* TLP MR address error */ 1015 u8 MRAddrLength_err:1; /* TLP MR length error */ 1016 u8 cpl_tag_err:1; /* TLP CPL tag error */ 1017 u8 cpl_status_err:1; /* TLP CPL status error */ 1018 u8 cpl_timeout_err:1; /* TLP CPL timeout */ 1019 u8 cci_parity_err:1; /* CCI bridge parity error */ 1020 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */ 1021 u64 rsvd:54; /* Reserved */ 1022 }; 1023 }; 1024 }; 1025 1026 /* FME First Error register */ 1027 struct feature_fme_first_error { 1028 #define FME_FIRST_ERROR_MASK ((1ULL << 60) - 1) 1029 union { 1030 u64 csr; 1031 struct { 1032 /* 1033 * Indicates the Error Register that was 1034 * triggered first 1035 */ 1036 u64 err_reg_status:60; 1037 /* 1038 * Holds 60 LSBs from the Error register that was 1039 * triggered first 1040 */ 1041 u8 errReg_id:4; 1042 }; 1043 }; 1044 }; 1045 1046 /* FME Next Error register */ 1047 struct feature_fme_next_error { 1048 #define FME_NEXT_ERROR_MASK ((1ULL << 60) - 1) 1049 union { 1050 u64 csr; 1051 struct { 1052 /* 1053 * Indicates the Error Register that was 1054 * triggered second 1055 */ 1056 u64 err_reg_status:60; 1057 /* 1058 * Holds 60 LSBs from the Error register that was 1059 * triggered second 1060 */ 1061 u8 errReg_id:4; 1062 }; 1063 }; 1064 }; 1065 1066 /* RAS Non Fatal Error Status register */ 1067 struct feature_fme_ras_nonfaterror { 1068 union { 1069 u64 csr; 1070 struct { 1071 /* thremal threshold AP1 */ 1072 u8 temp_thresh_ap1:1; 1073 /* thremal threshold AP2 */ 1074 u8 temp_thresh_ap2:1; 1075 u8 pcie_error:1; /* pcie Error */ 1076 u8 portfatal_error:1; /* port fatal error */ 1077 u8 proc_hot:1; /* Indicates a ProcHot event */ 1078 /* Indicates an AFU PF/VF access mismatch */ 1079 u8 afu_acc_mode_err:1; 1080 /* Injected nonfata Error */ 1081 u8 injected_nonfata_err:1; 1082 u8 rsvd1:2; 1083 /* Temperature threshold triggered AP6*/ 1084 u8 temp_thresh_AP6:1; 1085 /* Power threshold triggered AP1 */ 1086 u8 power_thresh_AP1:1; 1087 /* Power threshold triggered AP2 */ 1088 u8 power_thresh_AP2:1; 1089 /* Indicates a MBP event */ 1090 u8 mbp_err:1; 1091 u64 rsvd2:51; /* Reserved */ 1092 }; 1093 }; 1094 }; 1095 1096 /* RAS Catastrophic Fatal Error Status register */ 1097 struct feature_fme_ras_catfaterror { 1098 union { 1099 u64 csr; 1100 struct { 1101 /* KTI Link layer error detected */ 1102 u8 ktilink_fatal_err:1; 1103 /* tag-n-cache error detected */ 1104 u8 tagcch_fatal_err:1; 1105 /* CCI error detected */ 1106 u8 cci_fatal_err:1; 1107 /* KTI Protocol error detected */ 1108 u8 ktiprpto_fatal_err:1; 1109 /* Fatal DRAM error detected */ 1110 u8 dram_fatal_err:1; 1111 /* IOMMU detected */ 1112 u8 iommu_fatal_err:1; 1113 /* Fabric Fatal Error */ 1114 u8 fabric_fatal_err:1; 1115 /* PCIe possion Error */ 1116 u8 pcie_poison_err:1; 1117 /* Injected fatal Error */ 1118 u8 inject_fata_err:1; 1119 /* Catastrophic CRC Error */ 1120 u8 crc_catast_err:1; 1121 /* Catastrophic Thermal Error */ 1122 u8 therm_catast_err:1; 1123 /* Injected Catastrophic Error */ 1124 u8 injected_catast_err:1; 1125 /* SEU error on BMC */ 1126 u8 bmc_seu_catast_err:1; 1127 u64 rsvd:51; 1128 }; 1129 }; 1130 }; 1131 1132 /* RAS Error injection register */ 1133 struct feature_fme_ras_error_inj { 1134 #define FME_RAS_ERROR_INJ_MASK 0x7UL 1135 union { 1136 u64 csr; 1137 struct { 1138 u8 catast_error:1; /* Catastrophic error flag */ 1139 u8 fatal_error:1; /* Fatal error flag */ 1140 u8 nonfatal_error:1; /* NonFatal error flag */ 1141 u64 rsvd:61; /* Reserved */ 1142 }; 1143 }; 1144 }; 1145 1146 /* FME error capabilities */ 1147 struct feature_fme_error_capability { 1148 union { 1149 u64 csr; 1150 struct { 1151 u8 support_intr:1; 1152 /* MSI-X vector table entry number */ 1153 u16 intr_vector_num:12; 1154 u64 rsvd:50; /* Reserved */ 1155 u64 seu_support:1; 1156 }; 1157 }; 1158 }; 1159 1160 /* FME ERR FEATURE */ 1161 struct feature_fme_err { 1162 struct feature_header header; 1163 struct feature_fme_error0 fme_err_mask; 1164 struct feature_fme_error0 fme_err; 1165 struct feature_fme_pcie0_error pcie0_err_mask; 1166 struct feature_fme_pcie0_error pcie0_err; 1167 struct feature_fme_pcie1_error pcie1_err_mask; 1168 struct feature_fme_pcie1_error pcie1_err; 1169 struct feature_fme_first_error fme_first_err; 1170 struct feature_fme_next_error fme_next_err; 1171 struct feature_fme_ras_nonfaterror ras_nonfat_mask; 1172 struct feature_fme_ras_nonfaterror ras_nonfaterr; 1173 struct feature_fme_ras_catfaterror ras_catfat_mask; 1174 struct feature_fme_ras_catfaterror ras_catfaterr; 1175 struct feature_fme_ras_error_inj ras_error_inj; 1176 struct feature_fme_error_capability fme_err_capability; 1177 u64 seu_emr_l; 1178 u64 seu_emr_h; 1179 }; 1180 1181 /* FME Partial Reconfiguration Control */ 1182 struct feature_fme_pr_ctl { 1183 union { 1184 u64 csr; 1185 struct { 1186 u8 pr_reset:1; /* Reset PR Engine */ 1187 u8 rsvd3:3; /* Reserved */ 1188 u8 pr_reset_ack:1; /* Reset PR Engine Ack */ 1189 u8 rsvd4:3; /* Reserved */ 1190 u8 pr_regionid:2; /* PR Region ID */ 1191 u8 rsvd1:2; /* Reserved */ 1192 u8 pr_start_req:1; /* PR Start Request */ 1193 u8 pr_push_complete:1; /* PR Data push complete */ 1194 u8 pr_kind:1; /* PR Data push complete */ 1195 u32 rsvd:17; /* Reserved */ 1196 u32 config_data; /* Config data TBD */ 1197 }; 1198 }; 1199 }; 1200 1201 /* FME Partial Reconfiguration Status */ 1202 struct feature_fme_pr_status { 1203 union { 1204 u64 csr; 1205 struct { 1206 u16 pr_credit:9; /* PR Credits */ 1207 u8 rsvd2:7; /* Reserved */ 1208 u8 pr_status:1; /* PR status */ 1209 u8 rsvd:3; /* Reserved */ 1210 /* Altra PR Controller Block status */ 1211 u8 pr_controller_status:3; 1212 u8 rsvd1:1; /* Reserved */ 1213 u8 pr_host_status:4; /* PR Host status */ 1214 u8 rsvd3:4; /* Reserved */ 1215 /* Security Block Status fields (TBD) */ 1216 u32 security_bstatus; 1217 }; 1218 }; 1219 }; 1220 1221 /* FME Partial Reconfiguration Data */ 1222 struct feature_fme_pr_data { 1223 union { 1224 u64 csr; /* PR data from the raw-binary file */ 1225 struct { 1226 /* PR data from the raw-binary file */ 1227 u32 pr_data_raw; 1228 u32 rsvd; 1229 }; 1230 }; 1231 }; 1232 1233 /* FME PR Public Key */ 1234 struct feature_fme_pr_key { 1235 u64 key; /* FME PR Public Hash */ 1236 }; 1237 1238 /* FME PR FEATURE */ 1239 struct feature_fme_pr { 1240 struct feature_header header; 1241 /*Partial Reconfiguration control */ 1242 struct feature_fme_pr_ctl ccip_fme_pr_control; 1243 1244 /* Partial Reconfiguration Status */ 1245 struct feature_fme_pr_status ccip_fme_pr_status; 1246 1247 /* Partial Reconfiguration data */ 1248 struct feature_fme_pr_data ccip_fme_pr_data; 1249 1250 /* Partial Reconfiguration data */ 1251 u64 ccip_fme_pr_err; 1252 1253 u64 rsvd1[3]; 1254 1255 /* Partial Reconfiguration data registers */ 1256 u64 fme_pr_data1; 1257 u64 fme_pr_data2; 1258 u64 fme_pr_data3; 1259 u64 fme_pr_data4; 1260 u64 fme_pr_data5; 1261 u64 fme_pr_data6; 1262 u64 fme_pr_data7; 1263 u64 fme_pr_data8; 1264 1265 u64 rsvd2[5]; 1266 1267 /* PR Interface ID */ 1268 u64 fme_pr_intfc_id_l; 1269 u64 fme_pr_intfc_id_h; 1270 1271 /* MSIX filed to be Added */ 1272 }; 1273 1274 /* FME HSSI Control */ 1275 struct feature_fme_hssi_eth_ctrl { 1276 union { 1277 u64 csr; 1278 struct { 1279 u32 data:32; /* HSSI data */ 1280 u16 address:16; /* HSSI address */ 1281 /* 1282 * HSSI comamnd 1283 * 0x0 - No request 1284 * 0x08 - SW register RD request 1285 * 0x10 - SW register WR request 1286 * 0x40 - Auxiliar bus RD request 1287 * 0x80 - Auxiliar bus WR request 1288 */ 1289 u16 cmd:16; 1290 }; 1291 }; 1292 }; 1293 1294 /* FME HSSI Status */ 1295 struct feature_fme_hssi_eth_stat { 1296 union { 1297 u64 csr; 1298 struct { 1299 u32 data:32; /* HSSI data */ 1300 u8 acknowledge:1; /* HSSI acknowledge */ 1301 u8 spare:1; /* HSSI spare */ 1302 u32 rsvd:30; /* Reserved */ 1303 }; 1304 }; 1305 }; 1306 1307 /* FME HSSI FEATURE */ 1308 struct feature_fme_hssi { 1309 struct feature_header header; 1310 struct feature_fme_hssi_eth_ctrl hssi_control; 1311 struct feature_fme_hssi_eth_stat hssi_status; 1312 }; 1313 1314 #define PORT_ERR_MASK 0xfff0703ff001f 1315 struct feature_port_err_key { 1316 union { 1317 u64 csr; 1318 struct { 1319 /* Tx Channel0: Overflow */ 1320 u8 tx_ch0_overflow:1; 1321 /* Tx Channel0: Invalid request encoding */ 1322 u8 tx_ch0_invaldreq :1; 1323 /* Tx Channel0: Request with cl_len=3 not supported */ 1324 u8 tx_ch0_cl_len3:1; 1325 /* Tx Channel0: Request with cl_len=2 not aligned 2CL */ 1326 u8 tx_ch0_cl_len2:1; 1327 /* Tx Channel0: Request with cl_len=4 not aligned 4CL */ 1328 u8 tx_ch0_cl_len4:1; 1329 1330 u16 rsvd1:4; /* Reserved */ 1331 1332 /* AFU MMIO RD received while PORT is in reset */ 1333 u8 mmio_rd_whilerst:1; 1334 /* AFU MMIO WR received while PORT is in reset */ 1335 u8 mmio_wr_whilerst:1; 1336 1337 u16 rsvd2:5; /* Reserved */ 1338 1339 /* Tx Channel1: Overflow */ 1340 u8 tx_ch1_overflow:1; 1341 /* Tx Channel1: Invalid request encoding */ 1342 u8 tx_ch1_invaldreq:1; 1343 /* Tx Channel1: Request with cl_len=3 not supported */ 1344 u8 tx_ch1_cl_len3:1; 1345 /* Tx Channel1: Request with cl_len=2 not aligned 2CL */ 1346 u8 tx_ch1_cl_len2:1; 1347 /* Tx Channel1: Request with cl_len=4 not aligned 4CL */ 1348 u8 tx_ch1_cl_len4:1; 1349 1350 /* Tx Channel1: Insufficient data payload */ 1351 u8 tx_ch1_insuff_data:1; 1352 /* Tx Channel1: Data payload overrun */ 1353 u8 tx_ch1_data_overrun:1; 1354 /* Tx Channel1 : Incorrect address */ 1355 u8 tx_ch1_incorr_addr:1; 1356 /* Tx Channel1 : NON-Zero SOP Detected */ 1357 u8 tx_ch1_nzsop:1; 1358 /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */ 1359 u8 tx_ch1_illegal_vcsel:1; 1360 1361 u8 rsvd3:6; /* Reserved */ 1362 1363 /* MMIO Read Timeout in AFU */ 1364 u8 mmioread_timeout:1; 1365 1366 /* Tx Channel2: FIFO Overflow */ 1367 u8 tx_ch2_fifo_overflow:1; 1368 1369 /* MMIO read is not matching pending request */ 1370 u8 unexp_mmio_resp:1; 1371 1372 u8 rsvd4:5; /* Reserved */ 1373 1374 /* Number of pending Requests: counter overflow */ 1375 u8 tx_req_counter_overflow:1; 1376 /* Req with Address violating SMM Range */ 1377 u8 llpr_smrr_err:1; 1378 /* Req with Address violating second SMM Range */ 1379 u8 llpr_smrr2_err:1; 1380 /* Req with Address violating ME Stolen message */ 1381 u8 llpr_mesg_err:1; 1382 /* Req with Address violating Generic Protected Range */ 1383 u8 genprot_range_err:1; 1384 /* Req with Address violating Legacy Range low */ 1385 u8 legrange_low_err:1; 1386 /* Req with Address violating Legacy Range High */ 1387 u8 legrange_high_err:1; 1388 /* Req with Address violating VGA memory range */ 1389 u8 vgmem_range_err:1; 1390 u8 page_fault_err:1; /* Page fault */ 1391 u8 pmr_err:1; /* PMR Error */ 1392 u8 ap6_event:1; /* AP6 event */ 1393 /* VF FLR detected on Port with PF access control */ 1394 u8 vfflr_access_err:1; 1395 u16 rsvd5:12; /* Reserved */ 1396 }; 1397 }; 1398 }; 1399 1400 /* Port first error register, not contain all error bits in error register. */ 1401 struct feature_port_first_err_key { 1402 union { 1403 u64 csr; 1404 struct { 1405 u8 tx_ch0_overflow:1; 1406 u8 tx_ch0_invaldreq :1; 1407 u8 tx_ch0_cl_len3:1; 1408 u8 tx_ch0_cl_len2:1; 1409 u8 tx_ch0_cl_len4:1; 1410 u8 rsvd1:4; /* Reserved */ 1411 u8 mmio_rd_whilerst:1; 1412 u8 mmio_wr_whilerst:1; 1413 u8 rsvd2:5; /* Reserved */ 1414 u8 tx_ch1_overflow:1; 1415 u8 tx_ch1_invaldreq:1; 1416 u8 tx_ch1_cl_len3:1; 1417 u8 tx_ch1_cl_len2:1; 1418 u8 tx_ch1_cl_len4:1; 1419 u8 tx_ch1_insuff_data:1; 1420 u8 tx_ch1_data_overrun:1; 1421 u8 tx_ch1_incorr_addr:1; 1422 u8 tx_ch1_nzsop:1; 1423 u8 tx_ch1_illegal_vcsel:1; 1424 u8 rsvd3:6; /* Reserved */ 1425 u8 mmioread_timeout:1; 1426 u8 tx_ch2_fifo_overflow:1; 1427 u8 rsvd4:6; /* Reserved */ 1428 u8 tx_req_counter_overflow:1; 1429 u32 rsvd5:23; /* Reserved */ 1430 }; 1431 }; 1432 }; 1433 1434 /* Port malformed Req0 */ 1435 struct feature_port_malformed_req0 { 1436 u64 header_lsb; 1437 }; 1438 1439 /* Port malformed Req1 */ 1440 struct feature_port_malformed_req1 { 1441 u64 header_msb; 1442 }; 1443 1444 /* Port debug register */ 1445 struct feature_port_debug { 1446 u64 port_debug; 1447 }; 1448 1449 /* Port error capabilities */ 1450 struct feature_port_err_capability { 1451 union { 1452 u64 csr; 1453 struct { 1454 u8 support_intr:1; 1455 /* MSI-X vector table entry number */ 1456 u16 intr_vector_num:12; 1457 u64 rsvd:51; /* Reserved */ 1458 }; 1459 }; 1460 }; 1461 1462 /* PORT FEATURE ERROR */ 1463 struct feature_port_error { 1464 struct feature_header header; 1465 struct feature_port_err_key error_mask; 1466 struct feature_port_err_key port_error; 1467 struct feature_port_first_err_key port_first_error; 1468 struct feature_port_malformed_req0 malreq0; 1469 struct feature_port_malformed_req1 malreq1; 1470 struct feature_port_debug port_debug; 1471 struct feature_port_err_capability error_capability; 1472 }; 1473 1474 /* Port UMSG Capability */ 1475 struct feature_port_umsg_cap { 1476 union { 1477 u64 csr; 1478 struct { 1479 /* Number of umsg allocated to this port */ 1480 u8 umsg_allocated; 1481 /* Enable / Disable UMsg engine for this port */ 1482 u8 umsg_enable:1; 1483 /* Usmg initialization status */ 1484 u8 umsg_init_complete:1; 1485 /* IOMMU can not translate the umsg base address */ 1486 u8 umsg_trans_error:1; 1487 u64 rsvd:53; /* Reserved */ 1488 }; 1489 }; 1490 }; 1491 1492 /* Port UMSG base address */ 1493 struct feature_port_umsg_baseaddr { 1494 union { 1495 u64 csr; 1496 struct { 1497 u64 base_addr:48; /* 48 bit physical address */ 1498 u16 rsvd; /* Reserved */ 1499 }; 1500 }; 1501 }; 1502 1503 struct feature_port_umsg_mode { 1504 union { 1505 u64 csr; 1506 struct { 1507 u32 umsg_hint_enable; /* UMSG hint enable/disable */ 1508 u32 rsvd; /* Reserved */ 1509 }; 1510 }; 1511 }; 1512 1513 /* PORT FEATURE UMSG */ 1514 struct feature_port_umsg { 1515 struct feature_header header; 1516 struct feature_port_umsg_cap capability; 1517 struct feature_port_umsg_baseaddr baseaddr; 1518 struct feature_port_umsg_mode mode; 1519 }; 1520 1521 #define UMSG_EN_POLL_INVL 10 /* us */ 1522 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */ 1523 1524 /* Port UINT Capability */ 1525 struct feature_port_uint_cap { 1526 union { 1527 u64 csr; 1528 struct { 1529 u16 intr_num:12; /* Supported interrupts num */ 1530 /* First MSI-X vector table entry number */ 1531 u16 first_vec_num:12; 1532 u64 rsvd:40; 1533 }; 1534 }; 1535 }; 1536 1537 /* PORT FEATURE UINT */ 1538 struct feature_port_uint { 1539 struct feature_header header; 1540 struct feature_port_uint_cap capability; 1541 }; 1542 1543 /* STP region supports mmap operation, so use page aligned size. */ 1544 #define PORT_FEATURE_STP_REGION_SIZE \ 1545 IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp)) 1546 1547 /* Port STP status register (for debug only)*/ 1548 struct feature_port_stp_status { 1549 union { 1550 u64 csr; 1551 struct { 1552 /* SLD Hub end-point read/write timeout */ 1553 u8 sld_ep_timeout:1; 1554 /* Remote STP in reset/disable */ 1555 u8 rstp_disabled:1; 1556 u8 unsupported_read:1; 1557 /* MMIO timeout detected and faked with a response */ 1558 u8 mmio_timeout:1; 1559 u8 txfifo_count:4; 1560 u8 rxfifo_count:4; 1561 u8 txfifo_overflow:1; 1562 u8 txfifo_underflow:1; 1563 u8 rxfifo_overflow:1; 1564 u8 rxfifo_underflow:1; 1565 /* Number of MMIO write requests */ 1566 u16 write_requests; 1567 /* Number of MMIO read requests */ 1568 u16 read_requests; 1569 /* Number of MMIO read responses */ 1570 u16 read_responses; 1571 }; 1572 }; 1573 }; 1574 1575 /* 1576 * PORT FEATURE STP 1577 * Most registers in STP region are not touched by driver, but mmapped to user 1578 * space. So they are not defined in below data structure, as its actual size 1579 * is 0x18c per spec. 1580 */ 1581 struct feature_port_stp { 1582 struct feature_header header; 1583 struct feature_port_stp_status stp_status; 1584 }; 1585 1586 /** 1587 * enum fpga_pr_states - fpga PR states 1588 * @FPGA_PR_STATE_UNKNOWN: can't determine state 1589 * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming 1590 * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 1591 * @FPGA_PR_STATE_WRITE: writing image to FPGA 1592 * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA 1593 * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps 1594 * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 1595 * @FPGA_PR_STATE_OPERATING: FPGA PR done 1596 */ 1597 enum fpga_pr_states { 1598 /* canot determine state states */ 1599 FPGA_PR_STATE_UNKNOWN, 1600 1601 /* write sequence: init, write, complete */ 1602 FPGA_PR_STATE_WRITE_INIT, 1603 FPGA_PR_STATE_WRITE_INIT_ERR, 1604 FPGA_PR_STATE_WRITE, 1605 FPGA_PR_STATE_WRITE_ERR, 1606 FPGA_PR_STATE_WRITE_COMPLETE, 1607 FPGA_PR_STATE_WRITE_COMPLETE_ERR, 1608 1609 /* FPGA PR done */ 1610 FPGA_PR_STATE_DONE, 1611 }; 1612 1613 /* 1614 * FPGA Manager flags 1615 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 1616 */ 1617 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 1618 1619 /** 1620 * struct fpga_pr_info - specific information to a FPGA PR 1621 * @flags: boolean flags as defined above 1622 * @pr_err: PR error code 1623 * @state: fpga manager state 1624 * @port_id: port id 1625 */ 1626 struct fpga_pr_info { 1627 u32 flags; 1628 u64 pr_err; 1629 enum fpga_pr_states state; 1630 int port_id; 1631 }; 1632 1633 #define DEFINE_FPGA_PR_ERR_MSG(_name_) \ 1634 static const char * const _name_[] = { \ 1635 "PR operation error detected", \ 1636 "PR CRC error detected", \ 1637 "PR incompatiable bitstream error detected", \ 1638 "PR IP protocol error detected", \ 1639 "PR FIFO overflow error detected", \ 1640 "PR timeout error detected", \ 1641 "PR secure load error detected", \ 1642 } 1643 1644 #define RST_POLL_INVL 10 /* us */ 1645 #define RST_POLL_TIMEOUT 1000 /* us */ 1646 1647 #define PR_WAIT_TIMEOUT 15000000 1648 1649 #define PR_HOST_STATUS_IDLE 0 1650 #define PR_MAX_ERR_NUM 7 1651 1652 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg); 1653 1654 /* 1655 * green bitstream header must be byte-packed to match the 1656 * real file format. 1657 */ 1658 struct bts_header { 1659 u64 guid_h; 1660 u64 guid_l; 1661 u32 metadata_len; 1662 }; 1663 1664 #define GBS_GUID_H 0x414750466e6f6558 1665 #define GBS_GUID_L 0x31303076534247b7 1666 #define is_valid_bts(bts_hdr) \ 1667 (((bts_hdr)->guid_h == GBS_GUID_H) && \ 1668 ((bts_hdr)->guid_l == GBS_GUID_L)) 1669 1670 #define check_support(n) (n == 1 ? "support" : "no") 1671 1672 /* bitstream id definition */ 1673 struct fme_bitstream_id { 1674 union { 1675 u64 id; 1676 struct { 1677 u8 build_patch:8; 1678 u8 build_minor:8; 1679 u8 build_major:8; 1680 u8 fvl_bypass:1; 1681 u8 mac_lightweight:1; 1682 u8 disagregate:1; 1683 u8 lightweiht:1; 1684 u8 seu:1; 1685 u8 ptp:1; 1686 u8 reserve:2; 1687 u8 interface:4; 1688 u32 afu_revision:12; 1689 u8 patch:4; 1690 u8 minor:4; 1691 u8 major:4; 1692 u8 reserved:4; 1693 }; 1694 }; 1695 }; 1696 1697 enum board_interface { 1698 VC_8_10G = 0, 1699 VC_4_25G = 1, 1700 VC_2_1_25 = 2, 1701 VC_4_25G_2_25G = 3, 1702 VC_2_2_25G = 4, 1703 }; 1704 1705 enum pac_major { 1706 VISTA_CREEK = 0, 1707 RUSH_CREEK = 1, 1708 DARBY_CREEK = 2, 1709 }; 1710 1711 enum pac_minor { 1712 DCP_1_0 = 0, 1713 DCP_1_1 = 1, 1714 DCP_1_2 = 2, 1715 }; 1716 1717 struct opae_board_info { 1718 enum pac_major major; 1719 enum pac_minor minor; 1720 enum board_interface type; 1721 1722 /* PAC features */ 1723 u8 fvl_bypass; 1724 u8 mac_lightweight; 1725 u8 disaggregate; 1726 u8 lightweight; 1727 u8 seu; 1728 u8 ptp; 1729 1730 u32 max10_version; 1731 u32 nios_fw_version; 1732 u32 nums_of_retimer; 1733 u32 ports_per_retimer; 1734 u32 nums_of_fvl; 1735 u32 ports_per_fvl; 1736 }; 1737 1738 #pragma pack(pop) 1739 #endif /* _BASE_IFPGA_DEFINES_H_ */ 1740