1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2020 Intel Corporation 3 */ 4 5 #ifndef __DLB2_REGS_H 6 #define __DLB2_REGS_H 7 8 #include "dlb2_osdep_types.h" 9 10 #define DLB2_FUNC_PF_VF2PF_MAILBOX_BYTES 256 11 #define DLB2_FUNC_PF_VF2PF_MAILBOX(vf_id, x) \ 12 (0x1000 + 0x4 * (x) + (vf_id) * 0x10000) 13 #define DLB2_FUNC_PF_VF2PF_MAILBOX_RST 0x0 14 union dlb2_func_pf_vf2pf_mailbox { 15 struct { 16 u32 msg : 32; 17 } field; 18 u32 val; 19 }; 20 21 #define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR(vf_id) \ 22 (0x1f00 + (vf_id) * 0x10000) 23 #define DLB2_FUNC_PF_VF2PF_MAILBOX_ISR_RST 0x0 24 union dlb2_func_pf_vf2pf_mailbox_isr { 25 struct { 26 u32 vf0_isr : 1; 27 u32 vf1_isr : 1; 28 u32 vf2_isr : 1; 29 u32 vf3_isr : 1; 30 u32 vf4_isr : 1; 31 u32 vf5_isr : 1; 32 u32 vf6_isr : 1; 33 u32 vf7_isr : 1; 34 u32 vf8_isr : 1; 35 u32 vf9_isr : 1; 36 u32 vf10_isr : 1; 37 u32 vf11_isr : 1; 38 u32 vf12_isr : 1; 39 u32 vf13_isr : 1; 40 u32 vf14_isr : 1; 41 u32 vf15_isr : 1; 42 u32 rsvd0 : 16; 43 } field; 44 u32 val; 45 }; 46 47 #define DLB2_FUNC_PF_VF2PF_FLR_ISR(vf_id) \ 48 (0x1f04 + (vf_id) * 0x10000) 49 #define DLB2_FUNC_PF_VF2PF_FLR_ISR_RST 0x0 50 union dlb2_func_pf_vf2pf_flr_isr { 51 struct { 52 u32 vf0_isr : 1; 53 u32 vf1_isr : 1; 54 u32 vf2_isr : 1; 55 u32 vf3_isr : 1; 56 u32 vf4_isr : 1; 57 u32 vf5_isr : 1; 58 u32 vf6_isr : 1; 59 u32 vf7_isr : 1; 60 u32 vf8_isr : 1; 61 u32 vf9_isr : 1; 62 u32 vf10_isr : 1; 63 u32 vf11_isr : 1; 64 u32 vf12_isr : 1; 65 u32 vf13_isr : 1; 66 u32 vf14_isr : 1; 67 u32 vf15_isr : 1; 68 u32 rsvd0 : 16; 69 } field; 70 u32 val; 71 }; 72 73 #define DLB2_FUNC_PF_VF2PF_ISR_PEND(vf_id) \ 74 (0x1f10 + (vf_id) * 0x10000) 75 #define DLB2_FUNC_PF_VF2PF_ISR_PEND_RST 0x0 76 union dlb2_func_pf_vf2pf_isr_pend { 77 struct { 78 u32 isr_pend : 1; 79 u32 rsvd0 : 31; 80 } field; 81 u32 val; 82 }; 83 84 #define DLB2_FUNC_PF_PF2VF_MAILBOX_BYTES 64 85 #define DLB2_FUNC_PF_PF2VF_MAILBOX(vf_id, x) \ 86 (0x2000 + 0x4 * (x) + (vf_id) * 0x10000) 87 #define DLB2_FUNC_PF_PF2VF_MAILBOX_RST 0x0 88 union dlb2_func_pf_pf2vf_mailbox { 89 struct { 90 u32 msg : 32; 91 } field; 92 u32 val; 93 }; 94 95 #define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR(vf_id) \ 96 (0x2f00 + (vf_id) * 0x10000) 97 #define DLB2_FUNC_PF_PF2VF_MAILBOX_ISR_RST 0x0 98 union dlb2_func_pf_pf2vf_mailbox_isr { 99 struct { 100 u32 vf0_isr : 1; 101 u32 vf1_isr : 1; 102 u32 vf2_isr : 1; 103 u32 vf3_isr : 1; 104 u32 vf4_isr : 1; 105 u32 vf5_isr : 1; 106 u32 vf6_isr : 1; 107 u32 vf7_isr : 1; 108 u32 vf8_isr : 1; 109 u32 vf9_isr : 1; 110 u32 vf10_isr : 1; 111 u32 vf11_isr : 1; 112 u32 vf12_isr : 1; 113 u32 vf13_isr : 1; 114 u32 vf14_isr : 1; 115 u32 vf15_isr : 1; 116 u32 rsvd0 : 16; 117 } field; 118 u32 val; 119 }; 120 121 #define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS(vf_id) \ 122 (0x3000 + (vf_id) * 0x10000) 123 #define DLB2_FUNC_PF_VF_RESET_IN_PROGRESS_RST 0xffff 124 union dlb2_func_pf_vf_reset_in_progress { 125 struct { 126 u32 vf0_reset_in_progress : 1; 127 u32 vf1_reset_in_progress : 1; 128 u32 vf2_reset_in_progress : 1; 129 u32 vf3_reset_in_progress : 1; 130 u32 vf4_reset_in_progress : 1; 131 u32 vf5_reset_in_progress : 1; 132 u32 vf6_reset_in_progress : 1; 133 u32 vf7_reset_in_progress : 1; 134 u32 vf8_reset_in_progress : 1; 135 u32 vf9_reset_in_progress : 1; 136 u32 vf10_reset_in_progress : 1; 137 u32 vf11_reset_in_progress : 1; 138 u32 vf12_reset_in_progress : 1; 139 u32 vf13_reset_in_progress : 1; 140 u32 vf14_reset_in_progress : 1; 141 u32 vf15_reset_in_progress : 1; 142 u32 rsvd0 : 16; 143 } field; 144 u32 val; 145 }; 146 147 #define DLB2_MSIX_MEM_VECTOR_CTRL(x) \ 148 (0x100000c + (x) * 0x10) 149 #define DLB2_MSIX_MEM_VECTOR_CTRL_RST 0x1 150 union dlb2_msix_mem_vector_ctrl { 151 struct { 152 u32 vec_mask : 1; 153 u32 rsvd0 : 31; 154 } field; 155 u32 val; 156 }; 157 158 #define DLB2_IOSF_FUNC_VF_BAR_DSBL(x) \ 159 (0x20 + (x) * 0x4) 160 #define DLB2_IOSF_FUNC_VF_BAR_DSBL_RST 0x0 161 union dlb2_iosf_func_vf_bar_dsbl { 162 struct { 163 u32 func_vf_bar_dis : 1; 164 u32 rsvd0 : 31; 165 } field; 166 u32 val; 167 }; 168 169 #define DLB2_SYS_TOTAL_VAS 0x1000011c 170 #define DLB2_SYS_TOTAL_VAS_RST 0x20 171 union dlb2_sys_total_vas { 172 struct { 173 u32 total_vas : 32; 174 } field; 175 u32 val; 176 }; 177 178 #define DLB2_SYS_TOTAL_DIR_PORTS 0x10000118 179 #define DLB2_SYS_TOTAL_DIR_PORTS_RST 0x40 180 union dlb2_sys_total_dir_ports { 181 struct { 182 u32 total_dir_ports : 32; 183 } field; 184 u32 val; 185 }; 186 187 #define DLB2_SYS_TOTAL_LDB_PORTS 0x10000114 188 #define DLB2_SYS_TOTAL_LDB_PORTS_RST 0x40 189 union dlb2_sys_total_ldb_ports { 190 struct { 191 u32 total_ldb_ports : 32; 192 } field; 193 u32 val; 194 }; 195 196 #define DLB2_SYS_TOTAL_DIR_QID 0x10000110 197 #define DLB2_SYS_TOTAL_DIR_QID_RST 0x40 198 union dlb2_sys_total_dir_qid { 199 struct { 200 u32 total_dir_qid : 32; 201 } field; 202 u32 val; 203 }; 204 205 #define DLB2_SYS_TOTAL_LDB_QID 0x1000010c 206 #define DLB2_SYS_TOTAL_LDB_QID_RST 0x20 207 union dlb2_sys_total_ldb_qid { 208 struct { 209 u32 total_ldb_qid : 32; 210 } field; 211 u32 val; 212 }; 213 214 #define DLB2_SYS_TOTAL_DIR_CRDS 0x10000108 215 #define DLB2_SYS_TOTAL_DIR_CRDS_RST 0x1000 216 union dlb2_sys_total_dir_crds { 217 struct { 218 u32 total_dir_credits : 32; 219 } field; 220 u32 val; 221 }; 222 223 #define DLB2_SYS_TOTAL_LDB_CRDS 0x10000104 224 #define DLB2_SYS_TOTAL_LDB_CRDS_RST 0x2000 225 union dlb2_sys_total_ldb_crds { 226 struct { 227 u32 total_ldb_credits : 32; 228 } field; 229 u32 val; 230 }; 231 232 #define DLB2_SYS_ALARM_PF_SYND2 0x10000508 233 #define DLB2_SYS_ALARM_PF_SYND2_RST 0x0 234 union dlb2_sys_alarm_pf_synd2 { 235 struct { 236 u32 lock_id : 16; 237 u32 meas : 1; 238 u32 debug : 7; 239 u32 cq_pop : 1; 240 u32 qe_uhl : 1; 241 u32 qe_orsp : 1; 242 u32 qe_valid : 1; 243 u32 cq_int_rearm : 1; 244 u32 dsi_error : 1; 245 u32 rsvd0 : 2; 246 } field; 247 u32 val; 248 }; 249 250 #define DLB2_SYS_ALARM_PF_SYND1 0x10000504 251 #define DLB2_SYS_ALARM_PF_SYND1_RST 0x0 252 union dlb2_sys_alarm_pf_synd1 { 253 struct { 254 u32 dsi : 16; 255 u32 qid : 8; 256 u32 qtype : 2; 257 u32 qpri : 3; 258 u32 msg_type : 3; 259 } field; 260 u32 val; 261 }; 262 263 #define DLB2_SYS_ALARM_PF_SYND0 0x10000500 264 #define DLB2_SYS_ALARM_PF_SYND0_RST 0x0 265 union dlb2_sys_alarm_pf_synd0 { 266 struct { 267 u32 syndrome : 8; 268 u32 rtype : 2; 269 u32 rsvd0 : 3; 270 u32 is_ldb : 1; 271 u32 cls : 2; 272 u32 aid : 6; 273 u32 unit : 4; 274 u32 source : 4; 275 u32 more : 1; 276 u32 valid : 1; 277 } field; 278 u32 val; 279 }; 280 281 #define DLB2_SYS_VF_LDB_VPP_V(x) \ 282 (0x10000f00 + (x) * 0x1000) 283 #define DLB2_SYS_VF_LDB_VPP_V_RST 0x0 284 union dlb2_sys_vf_ldb_vpp_v { 285 struct { 286 u32 vpp_v : 1; 287 u32 rsvd0 : 31; 288 } field; 289 u32 val; 290 }; 291 292 #define DLB2_SYS_VF_LDB_VPP2PP(x) \ 293 (0x10000f04 + (x) * 0x1000) 294 #define DLB2_SYS_VF_LDB_VPP2PP_RST 0x0 295 union dlb2_sys_vf_ldb_vpp2pp { 296 struct { 297 u32 pp : 6; 298 u32 rsvd0 : 26; 299 } field; 300 u32 val; 301 }; 302 303 #define DLB2_SYS_VF_DIR_VPP_V(x) \ 304 (0x10000f08 + (x) * 0x1000) 305 #define DLB2_SYS_VF_DIR_VPP_V_RST 0x0 306 union dlb2_sys_vf_dir_vpp_v { 307 struct { 308 u32 vpp_v : 1; 309 u32 rsvd0 : 31; 310 } field; 311 u32 val; 312 }; 313 314 #define DLB2_SYS_VF_DIR_VPP2PP(x) \ 315 (0x10000f0c + (x) * 0x1000) 316 #define DLB2_SYS_VF_DIR_VPP2PP_RST 0x0 317 union dlb2_sys_vf_dir_vpp2pp { 318 struct { 319 u32 pp : 6; 320 u32 rsvd0 : 26; 321 } field; 322 u32 val; 323 }; 324 325 #define DLB2_SYS_VF_LDB_VQID_V(x) \ 326 (0x10000f10 + (x) * 0x1000) 327 #define DLB2_SYS_VF_LDB_VQID_V_RST 0x0 328 union dlb2_sys_vf_ldb_vqid_v { 329 struct { 330 u32 vqid_v : 1; 331 u32 rsvd0 : 31; 332 } field; 333 u32 val; 334 }; 335 336 #define DLB2_SYS_VF_LDB_VQID2QID(x) \ 337 (0x10000f14 + (x) * 0x1000) 338 #define DLB2_SYS_VF_LDB_VQID2QID_RST 0x0 339 union dlb2_sys_vf_ldb_vqid2qid { 340 struct { 341 u32 qid : 5; 342 u32 rsvd0 : 27; 343 } field; 344 u32 val; 345 }; 346 347 #define DLB2_SYS_LDB_QID2VQID(x) \ 348 (0x10000f18 + (x) * 0x1000) 349 #define DLB2_SYS_LDB_QID2VQID_RST 0x0 350 union dlb2_sys_ldb_qid2vqid { 351 struct { 352 u32 vqid : 5; 353 u32 rsvd0 : 27; 354 } field; 355 u32 val; 356 }; 357 358 #define DLB2_SYS_VF_DIR_VQID_V(x) \ 359 (0x10000f1c + (x) * 0x1000) 360 #define DLB2_SYS_VF_DIR_VQID_V_RST 0x0 361 union dlb2_sys_vf_dir_vqid_v { 362 struct { 363 u32 vqid_v : 1; 364 u32 rsvd0 : 31; 365 } field; 366 u32 val; 367 }; 368 369 #define DLB2_SYS_VF_DIR_VQID2QID(x) \ 370 (0x10000f20 + (x) * 0x1000) 371 #define DLB2_SYS_VF_DIR_VQID2QID_RST 0x0 372 union dlb2_sys_vf_dir_vqid2qid { 373 struct { 374 u32 qid : 6; 375 u32 rsvd0 : 26; 376 } field; 377 u32 val; 378 }; 379 380 #define DLB2_SYS_LDB_VASQID_V(x) \ 381 (0x10000f24 + (x) * 0x1000) 382 #define DLB2_SYS_LDB_VASQID_V_RST 0x0 383 union dlb2_sys_ldb_vasqid_v { 384 struct { 385 u32 vasqid_v : 1; 386 u32 rsvd0 : 31; 387 } field; 388 u32 val; 389 }; 390 391 #define DLB2_SYS_DIR_VASQID_V(x) \ 392 (0x10000f28 + (x) * 0x1000) 393 #define DLB2_SYS_DIR_VASQID_V_RST 0x0 394 union dlb2_sys_dir_vasqid_v { 395 struct { 396 u32 vasqid_v : 1; 397 u32 rsvd0 : 31; 398 } field; 399 u32 val; 400 }; 401 402 #define DLB2_SYS_ALARM_VF_SYND2(x) \ 403 (0x10000f48 + (x) * 0x1000) 404 #define DLB2_SYS_ALARM_VF_SYND2_RST 0x0 405 union dlb2_sys_alarm_vf_synd2 { 406 struct { 407 u32 lock_id : 16; 408 u32 debug : 8; 409 u32 cq_pop : 1; 410 u32 qe_uhl : 1; 411 u32 qe_orsp : 1; 412 u32 qe_valid : 1; 413 u32 isz : 1; 414 u32 dsi_error : 1; 415 u32 dlbrsvd : 2; 416 } field; 417 u32 val; 418 }; 419 420 #define DLB2_SYS_ALARM_VF_SYND1(x) \ 421 (0x10000f44 + (x) * 0x1000) 422 #define DLB2_SYS_ALARM_VF_SYND1_RST 0x0 423 union dlb2_sys_alarm_vf_synd1 { 424 struct { 425 u32 dsi : 16; 426 u32 qid : 8; 427 u32 qtype : 2; 428 u32 qpri : 3; 429 u32 msg_type : 3; 430 } field; 431 u32 val; 432 }; 433 434 #define DLB2_SYS_ALARM_VF_SYND0(x) \ 435 (0x10000f40 + (x) * 0x1000) 436 #define DLB2_SYS_ALARM_VF_SYND0_RST 0x0 437 union dlb2_sys_alarm_vf_synd0 { 438 struct { 439 u32 syndrome : 8; 440 u32 rtype : 2; 441 u32 vf_synd0_parity : 1; 442 u32 vf_synd1_parity : 1; 443 u32 vf_synd2_parity : 1; 444 u32 is_ldb : 1; 445 u32 cls : 2; 446 u32 aid : 6; 447 u32 unit : 4; 448 u32 source : 4; 449 u32 more : 1; 450 u32 valid : 1; 451 } field; 452 u32 val; 453 }; 454 455 #define DLB2_SYS_LDB_QID_CFG_V(x) \ 456 (0x10000f58 + (x) * 0x1000) 457 #define DLB2_SYS_LDB_QID_CFG_V_RST 0x0 458 union dlb2_sys_ldb_qid_cfg_v { 459 struct { 460 u32 sn_cfg_v : 1; 461 u32 fid_cfg_v : 1; 462 u32 rsvd0 : 30; 463 } field; 464 u32 val; 465 }; 466 467 #define DLB2_SYS_LDB_QID_ITS(x) \ 468 (0x10000f54 + (x) * 0x1000) 469 #define DLB2_SYS_LDB_QID_ITS_RST 0x0 470 union dlb2_sys_ldb_qid_its { 471 struct { 472 u32 qid_its : 1; 473 u32 rsvd0 : 31; 474 } field; 475 u32 val; 476 }; 477 478 #define DLB2_SYS_LDB_QID_V(x) \ 479 (0x10000f50 + (x) * 0x1000) 480 #define DLB2_SYS_LDB_QID_V_RST 0x0 481 union dlb2_sys_ldb_qid_v { 482 struct { 483 u32 qid_v : 1; 484 u32 rsvd0 : 31; 485 } field; 486 u32 val; 487 }; 488 489 #define DLB2_SYS_DIR_QID_ITS(x) \ 490 (0x10000f64 + (x) * 0x1000) 491 #define DLB2_SYS_DIR_QID_ITS_RST 0x0 492 union dlb2_sys_dir_qid_its { 493 struct { 494 u32 qid_its : 1; 495 u32 rsvd0 : 31; 496 } field; 497 u32 val; 498 }; 499 500 #define DLB2_SYS_DIR_QID_V(x) \ 501 (0x10000f60 + (x) * 0x1000) 502 #define DLB2_SYS_DIR_QID_V_RST 0x0 503 union dlb2_sys_dir_qid_v { 504 struct { 505 u32 qid_v : 1; 506 u32 rsvd0 : 31; 507 } field; 508 u32 val; 509 }; 510 511 #define DLB2_SYS_LDB_CQ_AI_DATA(x) \ 512 (0x10000fa8 + (x) * 0x1000) 513 #define DLB2_SYS_LDB_CQ_AI_DATA_RST 0x0 514 union dlb2_sys_ldb_cq_ai_data { 515 struct { 516 u32 cq_ai_data : 32; 517 } field; 518 u32 val; 519 }; 520 521 #define DLB2_SYS_LDB_CQ_AI_ADDR(x) \ 522 (0x10000fa4 + (x) * 0x1000) 523 #define DLB2_SYS_LDB_CQ_AI_ADDR_RST 0x0 524 union dlb2_sys_ldb_cq_ai_addr { 525 struct { 526 u32 rsvd1 : 2; 527 u32 cq_ai_addr : 18; 528 u32 rsvd0 : 12; 529 } field; 530 u32 val; 531 }; 532 533 #define DLB2_SYS_LDB_CQ_PASID(x) \ 534 (0x10000fa0 + (x) * 0x1000) 535 #define DLB2_SYS_LDB_CQ_PASID_RST 0x0 536 union dlb2_sys_ldb_cq_pasid { 537 struct { 538 u32 pasid : 20; 539 u32 exe_req : 1; 540 u32 priv_req : 1; 541 u32 fmt2 : 1; 542 u32 rsvd0 : 9; 543 } field; 544 u32 val; 545 }; 546 547 #define DLB2_SYS_LDB_CQ_AT(x) \ 548 (0x10000f9c + (x) * 0x1000) 549 #define DLB2_SYS_LDB_CQ_AT_RST 0x0 550 union dlb2_sys_ldb_cq_at { 551 struct { 552 u32 cq_at : 2; 553 u32 rsvd0 : 30; 554 } field; 555 u32 val; 556 }; 557 558 #define DLB2_SYS_LDB_CQ_ISR(x) \ 559 (0x10000f98 + (x) * 0x1000) 560 #define DLB2_SYS_LDB_CQ_ISR_RST 0x0 561 /* CQ Interrupt Modes */ 562 #define DLB2_CQ_ISR_MODE_DIS 0 563 #define DLB2_CQ_ISR_MODE_MSI 1 564 #define DLB2_CQ_ISR_MODE_MSIX 2 565 #define DLB2_CQ_ISR_MODE_ADI 3 566 union dlb2_sys_ldb_cq_isr { 567 struct { 568 u32 vector : 6; 569 u32 vf : 4; 570 u32 en_code : 2; 571 u32 rsvd0 : 20; 572 } field; 573 u32 val; 574 }; 575 576 #define DLB2_SYS_LDB_CQ2VF_PF_RO(x) \ 577 (0x10000f94 + (x) * 0x1000) 578 #define DLB2_SYS_LDB_CQ2VF_PF_RO_RST 0x0 579 union dlb2_sys_ldb_cq2vf_pf_ro { 580 struct { 581 u32 vf : 4; 582 u32 is_pf : 1; 583 u32 ro : 1; 584 u32 rsvd0 : 26; 585 } field; 586 u32 val; 587 }; 588 589 #define DLB2_SYS_LDB_PP_V(x) \ 590 (0x10000f90 + (x) * 0x1000) 591 #define DLB2_SYS_LDB_PP_V_RST 0x0 592 union dlb2_sys_ldb_pp_v { 593 struct { 594 u32 pp_v : 1; 595 u32 rsvd0 : 31; 596 } field; 597 u32 val; 598 }; 599 600 #define DLB2_SYS_LDB_PP2VDEV(x) \ 601 (0x10000f8c + (x) * 0x1000) 602 #define DLB2_SYS_LDB_PP2VDEV_RST 0x0 603 union dlb2_sys_ldb_pp2vdev { 604 struct { 605 u32 vdev : 4; 606 u32 rsvd0 : 28; 607 } field; 608 u32 val; 609 }; 610 611 #define DLB2_SYS_LDB_PP2VAS(x) \ 612 (0x10000f88 + (x) * 0x1000) 613 #define DLB2_SYS_LDB_PP2VAS_RST 0x0 614 union dlb2_sys_ldb_pp2vas { 615 struct { 616 u32 vas : 5; 617 u32 rsvd0 : 27; 618 } field; 619 u32 val; 620 }; 621 622 #define DLB2_SYS_LDB_CQ_ADDR_U(x) \ 623 (0x10000f84 + (x) * 0x1000) 624 #define DLB2_SYS_LDB_CQ_ADDR_U_RST 0x0 625 union dlb2_sys_ldb_cq_addr_u { 626 struct { 627 u32 addr_u : 32; 628 } field; 629 u32 val; 630 }; 631 632 #define DLB2_SYS_LDB_CQ_ADDR_L(x) \ 633 (0x10000f80 + (x) * 0x1000) 634 #define DLB2_SYS_LDB_CQ_ADDR_L_RST 0x0 635 union dlb2_sys_ldb_cq_addr_l { 636 struct { 637 u32 rsvd0 : 6; 638 u32 addr_l : 26; 639 } field; 640 u32 val; 641 }; 642 643 #define DLB2_SYS_DIR_CQ_FMT(x) \ 644 (0x10000fec + (x) * 0x1000) 645 #define DLB2_SYS_DIR_CQ_FMT_RST 0x0 646 union dlb2_sys_dir_cq_fmt { 647 struct { 648 u32 keep_pf_ppid : 1; 649 u32 rsvd0 : 31; 650 } field; 651 u32 val; 652 }; 653 654 #define DLB2_SYS_DIR_CQ_AI_DATA(x) \ 655 (0x10000fe8 + (x) * 0x1000) 656 #define DLB2_SYS_DIR_CQ_AI_DATA_RST 0x0 657 union dlb2_sys_dir_cq_ai_data { 658 struct { 659 u32 cq_ai_data : 32; 660 } field; 661 u32 val; 662 }; 663 664 #define DLB2_SYS_DIR_CQ_AI_ADDR(x) \ 665 (0x10000fe4 + (x) * 0x1000) 666 #define DLB2_SYS_DIR_CQ_AI_ADDR_RST 0x0 667 union dlb2_sys_dir_cq_ai_addr { 668 struct { 669 u32 rsvd1 : 2; 670 u32 cq_ai_addr : 18; 671 u32 rsvd0 : 12; 672 } field; 673 u32 val; 674 }; 675 676 #define DLB2_SYS_DIR_CQ_PASID(x) \ 677 (0x10000fe0 + (x) * 0x1000) 678 #define DLB2_SYS_DIR_CQ_PASID_RST 0x0 679 union dlb2_sys_dir_cq_pasid { 680 struct { 681 u32 pasid : 20; 682 u32 exe_req : 1; 683 u32 priv_req : 1; 684 u32 fmt2 : 1; 685 u32 rsvd0 : 9; 686 } field; 687 u32 val; 688 }; 689 690 #define DLB2_SYS_DIR_CQ_AT(x) \ 691 (0x10000fdc + (x) * 0x1000) 692 #define DLB2_SYS_DIR_CQ_AT_RST 0x0 693 union dlb2_sys_dir_cq_at { 694 struct { 695 u32 cq_at : 2; 696 u32 rsvd0 : 30; 697 } field; 698 u32 val; 699 }; 700 701 #define DLB2_SYS_DIR_CQ_ISR(x) \ 702 (0x10000fd8 + (x) * 0x1000) 703 #define DLB2_SYS_DIR_CQ_ISR_RST 0x0 704 union dlb2_sys_dir_cq_isr { 705 struct { 706 u32 vector : 6; 707 u32 vf : 4; 708 u32 en_code : 2; 709 u32 rsvd0 : 20; 710 } field; 711 u32 val; 712 }; 713 714 #define DLB2_SYS_DIR_CQ2VF_PF_RO(x) \ 715 (0x10000fd4 + (x) * 0x1000) 716 #define DLB2_SYS_DIR_CQ2VF_PF_RO_RST 0x0 717 union dlb2_sys_dir_cq2vf_pf_ro { 718 struct { 719 u32 vf : 4; 720 u32 is_pf : 1; 721 u32 ro : 1; 722 u32 rsvd0 : 26; 723 } field; 724 u32 val; 725 }; 726 727 #define DLB2_SYS_DIR_PP_V(x) \ 728 (0x10000fd0 + (x) * 0x1000) 729 #define DLB2_SYS_DIR_PP_V_RST 0x0 730 union dlb2_sys_dir_pp_v { 731 struct { 732 u32 pp_v : 1; 733 u32 rsvd0 : 31; 734 } field; 735 u32 val; 736 }; 737 738 #define DLB2_SYS_DIR_PP2VDEV(x) \ 739 (0x10000fcc + (x) * 0x1000) 740 #define DLB2_SYS_DIR_PP2VDEV_RST 0x0 741 union dlb2_sys_dir_pp2vdev { 742 struct { 743 u32 vdev : 4; 744 u32 rsvd0 : 28; 745 } field; 746 u32 val; 747 }; 748 749 #define DLB2_SYS_DIR_PP2VAS(x) \ 750 (0x10000fc8 + (x) * 0x1000) 751 #define DLB2_SYS_DIR_PP2VAS_RST 0x0 752 union dlb2_sys_dir_pp2vas { 753 struct { 754 u32 vas : 5; 755 u32 rsvd0 : 27; 756 } field; 757 u32 val; 758 }; 759 760 #define DLB2_SYS_DIR_CQ_ADDR_U(x) \ 761 (0x10000fc4 + (x) * 0x1000) 762 #define DLB2_SYS_DIR_CQ_ADDR_U_RST 0x0 763 union dlb2_sys_dir_cq_addr_u { 764 struct { 765 u32 addr_u : 32; 766 } field; 767 u32 val; 768 }; 769 770 #define DLB2_SYS_DIR_CQ_ADDR_L(x) \ 771 (0x10000fc0 + (x) * 0x1000) 772 #define DLB2_SYS_DIR_CQ_ADDR_L_RST 0x0 773 union dlb2_sys_dir_cq_addr_l { 774 struct { 775 u32 rsvd0 : 6; 776 u32 addr_l : 26; 777 } field; 778 u32 val; 779 }; 780 781 #define DLB2_SYS_INGRESS_ALARM_ENBL 0x10000300 782 #define DLB2_SYS_INGRESS_ALARM_ENBL_RST 0x0 783 union dlb2_sys_ingress_alarm_enbl { 784 struct { 785 u32 illegal_hcw : 1; 786 u32 illegal_pp : 1; 787 u32 illegal_pasid : 1; 788 u32 illegal_qid : 1; 789 u32 disabled_qid : 1; 790 u32 illegal_ldb_qid_cfg : 1; 791 u32 rsvd0 : 26; 792 } field; 793 u32 val; 794 }; 795 796 #define DLB2_SYS_MSIX_ACK 0x10000400 797 #define DLB2_SYS_MSIX_ACK_RST 0x0 798 union dlb2_sys_msix_ack { 799 struct { 800 u32 msix_0_ack : 1; 801 u32 msix_1_ack : 1; 802 u32 rsvd0 : 30; 803 } field; 804 u32 val; 805 }; 806 807 #define DLB2_SYS_MSIX_PASSTHRU 0x10000404 808 #define DLB2_SYS_MSIX_PASSTHRU_RST 0x0 809 union dlb2_sys_msix_passthru { 810 struct { 811 u32 msix_0_passthru : 1; 812 u32 msix_1_passthru : 1; 813 u32 rsvd0 : 30; 814 } field; 815 u32 val; 816 }; 817 818 #define DLB2_SYS_MSIX_MODE 0x10000408 819 #define DLB2_SYS_MSIX_MODE_RST 0x0 820 /* MSI-X Modes */ 821 #define DLB2_MSIX_MODE_PACKED 0 822 #define DLB2_MSIX_MODE_COMPRESSED 1 823 union dlb2_sys_msix_mode { 824 struct { 825 u32 mode : 1; 826 u32 poll_mode : 1; 827 u32 poll_mask : 1; 828 u32 poll_lock : 1; 829 u32 rsvd0 : 28; 830 } field; 831 u32 val; 832 }; 833 834 #define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS 0x10000440 835 #define DLB2_SYS_DIR_CQ_31_0_OCC_INT_STS_RST 0x0 836 union dlb2_sys_dir_cq_31_0_occ_int_sts { 837 struct { 838 u32 cq_0_occ_int : 1; 839 u32 cq_1_occ_int : 1; 840 u32 cq_2_occ_int : 1; 841 u32 cq_3_occ_int : 1; 842 u32 cq_4_occ_int : 1; 843 u32 cq_5_occ_int : 1; 844 u32 cq_6_occ_int : 1; 845 u32 cq_7_occ_int : 1; 846 u32 cq_8_occ_int : 1; 847 u32 cq_9_occ_int : 1; 848 u32 cq_10_occ_int : 1; 849 u32 cq_11_occ_int : 1; 850 u32 cq_12_occ_int : 1; 851 u32 cq_13_occ_int : 1; 852 u32 cq_14_occ_int : 1; 853 u32 cq_15_occ_int : 1; 854 u32 cq_16_occ_int : 1; 855 u32 cq_17_occ_int : 1; 856 u32 cq_18_occ_int : 1; 857 u32 cq_19_occ_int : 1; 858 u32 cq_20_occ_int : 1; 859 u32 cq_21_occ_int : 1; 860 u32 cq_22_occ_int : 1; 861 u32 cq_23_occ_int : 1; 862 u32 cq_24_occ_int : 1; 863 u32 cq_25_occ_int : 1; 864 u32 cq_26_occ_int : 1; 865 u32 cq_27_occ_int : 1; 866 u32 cq_28_occ_int : 1; 867 u32 cq_29_occ_int : 1; 868 u32 cq_30_occ_int : 1; 869 u32 cq_31_occ_int : 1; 870 } field; 871 u32 val; 872 }; 873 874 #define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS 0x10000444 875 #define DLB2_SYS_DIR_CQ_63_32_OCC_INT_STS_RST 0x0 876 union dlb2_sys_dir_cq_63_32_occ_int_sts { 877 struct { 878 u32 cq_32_occ_int : 1; 879 u32 cq_33_occ_int : 1; 880 u32 cq_34_occ_int : 1; 881 u32 cq_35_occ_int : 1; 882 u32 cq_36_occ_int : 1; 883 u32 cq_37_occ_int : 1; 884 u32 cq_38_occ_int : 1; 885 u32 cq_39_occ_int : 1; 886 u32 cq_40_occ_int : 1; 887 u32 cq_41_occ_int : 1; 888 u32 cq_42_occ_int : 1; 889 u32 cq_43_occ_int : 1; 890 u32 cq_44_occ_int : 1; 891 u32 cq_45_occ_int : 1; 892 u32 cq_46_occ_int : 1; 893 u32 cq_47_occ_int : 1; 894 u32 cq_48_occ_int : 1; 895 u32 cq_49_occ_int : 1; 896 u32 cq_50_occ_int : 1; 897 u32 cq_51_occ_int : 1; 898 u32 cq_52_occ_int : 1; 899 u32 cq_53_occ_int : 1; 900 u32 cq_54_occ_int : 1; 901 u32 cq_55_occ_int : 1; 902 u32 cq_56_occ_int : 1; 903 u32 cq_57_occ_int : 1; 904 u32 cq_58_occ_int : 1; 905 u32 cq_59_occ_int : 1; 906 u32 cq_60_occ_int : 1; 907 u32 cq_61_occ_int : 1; 908 u32 cq_62_occ_int : 1; 909 u32 cq_63_occ_int : 1; 910 } field; 911 u32 val; 912 }; 913 914 #define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS 0x10000460 915 #define DLB2_SYS_LDB_CQ_31_0_OCC_INT_STS_RST 0x0 916 union dlb2_sys_ldb_cq_31_0_occ_int_sts { 917 struct { 918 u32 cq_0_occ_int : 1; 919 u32 cq_1_occ_int : 1; 920 u32 cq_2_occ_int : 1; 921 u32 cq_3_occ_int : 1; 922 u32 cq_4_occ_int : 1; 923 u32 cq_5_occ_int : 1; 924 u32 cq_6_occ_int : 1; 925 u32 cq_7_occ_int : 1; 926 u32 cq_8_occ_int : 1; 927 u32 cq_9_occ_int : 1; 928 u32 cq_10_occ_int : 1; 929 u32 cq_11_occ_int : 1; 930 u32 cq_12_occ_int : 1; 931 u32 cq_13_occ_int : 1; 932 u32 cq_14_occ_int : 1; 933 u32 cq_15_occ_int : 1; 934 u32 cq_16_occ_int : 1; 935 u32 cq_17_occ_int : 1; 936 u32 cq_18_occ_int : 1; 937 u32 cq_19_occ_int : 1; 938 u32 cq_20_occ_int : 1; 939 u32 cq_21_occ_int : 1; 940 u32 cq_22_occ_int : 1; 941 u32 cq_23_occ_int : 1; 942 u32 cq_24_occ_int : 1; 943 u32 cq_25_occ_int : 1; 944 u32 cq_26_occ_int : 1; 945 u32 cq_27_occ_int : 1; 946 u32 cq_28_occ_int : 1; 947 u32 cq_29_occ_int : 1; 948 u32 cq_30_occ_int : 1; 949 u32 cq_31_occ_int : 1; 950 } field; 951 u32 val; 952 }; 953 954 #define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS 0x10000464 955 #define DLB2_SYS_LDB_CQ_63_32_OCC_INT_STS_RST 0x0 956 union dlb2_sys_ldb_cq_63_32_occ_int_sts { 957 struct { 958 u32 cq_32_occ_int : 1; 959 u32 cq_33_occ_int : 1; 960 u32 cq_34_occ_int : 1; 961 u32 cq_35_occ_int : 1; 962 u32 cq_36_occ_int : 1; 963 u32 cq_37_occ_int : 1; 964 u32 cq_38_occ_int : 1; 965 u32 cq_39_occ_int : 1; 966 u32 cq_40_occ_int : 1; 967 u32 cq_41_occ_int : 1; 968 u32 cq_42_occ_int : 1; 969 u32 cq_43_occ_int : 1; 970 u32 cq_44_occ_int : 1; 971 u32 cq_45_occ_int : 1; 972 u32 cq_46_occ_int : 1; 973 u32 cq_47_occ_int : 1; 974 u32 cq_48_occ_int : 1; 975 u32 cq_49_occ_int : 1; 976 u32 cq_50_occ_int : 1; 977 u32 cq_51_occ_int : 1; 978 u32 cq_52_occ_int : 1; 979 u32 cq_53_occ_int : 1; 980 u32 cq_54_occ_int : 1; 981 u32 cq_55_occ_int : 1; 982 u32 cq_56_occ_int : 1; 983 u32 cq_57_occ_int : 1; 984 u32 cq_58_occ_int : 1; 985 u32 cq_59_occ_int : 1; 986 u32 cq_60_occ_int : 1; 987 u32 cq_61_occ_int : 1; 988 u32 cq_62_occ_int : 1; 989 u32 cq_63_occ_int : 1; 990 } field; 991 u32 val; 992 }; 993 994 #define DLB2_SYS_DIR_CQ_OPT_CLR 0x100004c0 995 #define DLB2_SYS_DIR_CQ_OPT_CLR_RST 0x0 996 union dlb2_sys_dir_cq_opt_clr { 997 struct { 998 u32 cq : 6; 999 u32 rsvd0 : 26; 1000 } field; 1001 u32 val; 1002 }; 1003 1004 #define DLB2_SYS_ALARM_HW_SYND 0x1000050c 1005 #define DLB2_SYS_ALARM_HW_SYND_RST 0x0 1006 union dlb2_sys_alarm_hw_synd { 1007 struct { 1008 u32 syndrome : 8; 1009 u32 rtype : 2; 1010 u32 alarm : 1; 1011 u32 cwd : 1; 1012 u32 vf_pf_mb : 1; 1013 u32 rsvd0 : 1; 1014 u32 cls : 2; 1015 u32 aid : 6; 1016 u32 unit : 4; 1017 u32 source : 4; 1018 u32 more : 1; 1019 u32 valid : 1; 1020 } field; 1021 u32 val; 1022 }; 1023 1024 #define DLB2_AQED_PIPE_QID_FID_LIM(x) \ 1025 (0x20000000 + (x) * 0x1000) 1026 #define DLB2_AQED_PIPE_QID_FID_LIM_RST 0x7ff 1027 union dlb2_aqed_pipe_qid_fid_lim { 1028 struct { 1029 u32 qid_fid_limit : 13; 1030 u32 rsvd0 : 19; 1031 } field; 1032 u32 val; 1033 }; 1034 1035 #define DLB2_AQED_PIPE_QID_HID_WIDTH(x) \ 1036 (0x20080000 + (x) * 0x1000) 1037 #define DLB2_AQED_PIPE_QID_HID_WIDTH_RST 0x0 1038 union dlb2_aqed_pipe_qid_hid_width { 1039 struct { 1040 u32 compress_code : 3; 1041 u32 rsvd0 : 29; 1042 } field; 1043 u32 val; 1044 }; 1045 1046 #define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0 0x24000004 1047 #define DLB2_AQED_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATM_0_RST 0xfefcfaf8 1048 union dlb2_aqed_pipe_cfg_arb_weights_tqpri_atm_0 { 1049 struct { 1050 u32 pri0 : 8; 1051 u32 pri1 : 8; 1052 u32 pri2 : 8; 1053 u32 pri3 : 8; 1054 } field; 1055 u32 val; 1056 }; 1057 1058 #define DLB2_ATM_QID2CQIDIX_00(x) \ 1059 (0x30080000 + (x) * 0x1000) 1060 #define DLB2_ATM_QID2CQIDIX_00_RST 0x0 1061 #define DLB2_ATM_QID2CQIDIX(x, y) \ 1062 (DLB2_ATM_QID2CQIDIX_00(x) + 0x80000 * (y)) 1063 #define DLB2_ATM_QID2CQIDIX_NUM 16 1064 union dlb2_atm_qid2cqidix_00 { 1065 struct { 1066 u32 cq_p0 : 8; 1067 u32 cq_p1 : 8; 1068 u32 cq_p2 : 8; 1069 u32 cq_p3 : 8; 1070 } field; 1071 u32 val; 1072 }; 1073 1074 #define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN 0x34000004 1075 #define DLB2_ATM_CFG_ARB_WEIGHTS_RDY_BIN_RST 0xfffefdfc 1076 union dlb2_atm_cfg_arb_weights_rdy_bin { 1077 struct { 1078 u32 bin0 : 8; 1079 u32 bin1 : 8; 1080 u32 bin2 : 8; 1081 u32 bin3 : 8; 1082 } field; 1083 u32 val; 1084 }; 1085 1086 #define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN 0x34000008 1087 #define DLB2_ATM_CFG_ARB_WEIGHTS_SCHED_BIN_RST 0xfffefdfc 1088 union dlb2_atm_cfg_arb_weights_sched_bin { 1089 struct { 1090 u32 bin0 : 8; 1091 u32 bin1 : 8; 1092 u32 bin2 : 8; 1093 u32 bin3 : 8; 1094 } field; 1095 u32 val; 1096 }; 1097 1098 #define DLB2_CHP_CFG_DIR_VAS_CRD(x) \ 1099 (0x40000000 + (x) * 0x1000) 1100 #define DLB2_CHP_CFG_DIR_VAS_CRD_RST 0x0 1101 union dlb2_chp_cfg_dir_vas_crd { 1102 struct { 1103 u32 count : 14; 1104 u32 rsvd0 : 18; 1105 } field; 1106 u32 val; 1107 }; 1108 1109 #define DLB2_CHP_CFG_LDB_VAS_CRD(x) \ 1110 (0x40080000 + (x) * 0x1000) 1111 #define DLB2_CHP_CFG_LDB_VAS_CRD_RST 0x0 1112 union dlb2_chp_cfg_ldb_vas_crd { 1113 struct { 1114 u32 count : 15; 1115 u32 rsvd0 : 17; 1116 } field; 1117 u32 val; 1118 }; 1119 1120 #define DLB2_CHP_ORD_QID_SN(x) \ 1121 (0x40100000 + (x) * 0x1000) 1122 #define DLB2_CHP_ORD_QID_SN_RST 0x0 1123 union dlb2_chp_ord_qid_sn { 1124 struct { 1125 u32 sn : 10; 1126 u32 rsvd0 : 22; 1127 } field; 1128 u32 val; 1129 }; 1130 1131 #define DLB2_CHP_ORD_QID_SN_MAP(x) \ 1132 (0x40180000 + (x) * 0x1000) 1133 #define DLB2_CHP_ORD_QID_SN_MAP_RST 0x0 1134 union dlb2_chp_ord_qid_sn_map { 1135 struct { 1136 u32 mode : 3; 1137 u32 slot : 4; 1138 u32 rsvz0 : 1; 1139 u32 grp : 1; 1140 u32 rsvz1 : 1; 1141 u32 rsvd0 : 22; 1142 } field; 1143 u32 val; 1144 }; 1145 1146 #define DLB2_CHP_SN_CHK_ENBL(x) \ 1147 (0x40200000 + (x) * 0x1000) 1148 #define DLB2_CHP_SN_CHK_ENBL_RST 0x0 1149 union dlb2_chp_sn_chk_enbl { 1150 struct { 1151 u32 en : 1; 1152 u32 rsvd0 : 31; 1153 } field; 1154 u32 val; 1155 }; 1156 1157 #define DLB2_CHP_DIR_CQ_DEPTH(x) \ 1158 (0x40280000 + (x) * 0x1000) 1159 #define DLB2_CHP_DIR_CQ_DEPTH_RST 0x0 1160 union dlb2_chp_dir_cq_depth { 1161 struct { 1162 u32 depth : 13; 1163 u32 rsvd0 : 19; 1164 } field; 1165 u32 val; 1166 }; 1167 1168 #define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH(x) \ 1169 (0x40300000 + (x) * 0x1000) 1170 #define DLB2_CHP_DIR_CQ_INT_DEPTH_THRSH_RST 0x0 1171 union dlb2_chp_dir_cq_int_depth_thrsh { 1172 struct { 1173 u32 depth_threshold : 13; 1174 u32 rsvd0 : 19; 1175 } field; 1176 u32 val; 1177 }; 1178 1179 #define DLB2_CHP_DIR_CQ_INT_ENB(x) \ 1180 (0x40380000 + (x) * 0x1000) 1181 #define DLB2_CHP_DIR_CQ_INT_ENB_RST 0x0 1182 union dlb2_chp_dir_cq_int_enb { 1183 struct { 1184 u32 en_tim : 1; 1185 u32 en_depth : 1; 1186 u32 rsvd0 : 30; 1187 } field; 1188 u32 val; 1189 }; 1190 1191 #define DLB2_CHP_DIR_CQ_TMR_THRSH(x) \ 1192 (0x40480000 + (x) * 0x1000) 1193 #define DLB2_CHP_DIR_CQ_TMR_THRSH_RST 0x1 1194 union dlb2_chp_dir_cq_tmr_thrsh { 1195 struct { 1196 u32 thrsh_0 : 1; 1197 u32 thrsh_13_1 : 13; 1198 u32 rsvd0 : 18; 1199 } field; 1200 u32 val; 1201 }; 1202 1203 #define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(x) \ 1204 (0x40500000 + (x) * 0x1000) 1205 #define DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL_RST 0x0 1206 union dlb2_chp_dir_cq_tkn_depth_sel { 1207 struct { 1208 u32 token_depth_select : 4; 1209 u32 rsvd0 : 28; 1210 } field; 1211 u32 val; 1212 }; 1213 1214 #define DLB2_CHP_DIR_CQ_WD_ENB(x) \ 1215 (0x40580000 + (x) * 0x1000) 1216 #define DLB2_CHP_DIR_CQ_WD_ENB_RST 0x0 1217 union dlb2_chp_dir_cq_wd_enb { 1218 struct { 1219 u32 wd_enable : 1; 1220 u32 rsvd0 : 31; 1221 } field; 1222 u32 val; 1223 }; 1224 1225 #define DLB2_CHP_DIR_CQ_WPTR(x) \ 1226 (0x40600000 + (x) * 0x1000) 1227 #define DLB2_CHP_DIR_CQ_WPTR_RST 0x0 1228 union dlb2_chp_dir_cq_wptr { 1229 struct { 1230 u32 write_pointer : 13; 1231 u32 rsvd0 : 19; 1232 } field; 1233 u32 val; 1234 }; 1235 1236 #define DLB2_CHP_DIR_CQ2VAS(x) \ 1237 (0x40680000 + (x) * 0x1000) 1238 #define DLB2_CHP_DIR_CQ2VAS_RST 0x0 1239 union dlb2_chp_dir_cq2vas { 1240 struct { 1241 u32 cq2vas : 5; 1242 u32 rsvd0 : 27; 1243 } field; 1244 u32 val; 1245 }; 1246 1247 #define DLB2_CHP_HIST_LIST_BASE(x) \ 1248 (0x40700000 + (x) * 0x1000) 1249 #define DLB2_CHP_HIST_LIST_BASE_RST 0x0 1250 union dlb2_chp_hist_list_base { 1251 struct { 1252 u32 base : 13; 1253 u32 rsvd0 : 19; 1254 } field; 1255 u32 val; 1256 }; 1257 1258 #define DLB2_CHP_HIST_LIST_LIM(x) \ 1259 (0x40780000 + (x) * 0x1000) 1260 #define DLB2_CHP_HIST_LIST_LIM_RST 0x0 1261 union dlb2_chp_hist_list_lim { 1262 struct { 1263 u32 limit : 13; 1264 u32 rsvd0 : 19; 1265 } field; 1266 u32 val; 1267 }; 1268 1269 #define DLB2_CHP_HIST_LIST_POP_PTR(x) \ 1270 (0x40800000 + (x) * 0x1000) 1271 #define DLB2_CHP_HIST_LIST_POP_PTR_RST 0x0 1272 union dlb2_chp_hist_list_pop_ptr { 1273 struct { 1274 u32 pop_ptr : 13; 1275 u32 generation : 1; 1276 u32 rsvd0 : 18; 1277 } field; 1278 u32 val; 1279 }; 1280 1281 #define DLB2_CHP_HIST_LIST_PUSH_PTR(x) \ 1282 (0x40880000 + (x) * 0x1000) 1283 #define DLB2_CHP_HIST_LIST_PUSH_PTR_RST 0x0 1284 union dlb2_chp_hist_list_push_ptr { 1285 struct { 1286 u32 push_ptr : 13; 1287 u32 generation : 1; 1288 u32 rsvd0 : 18; 1289 } field; 1290 u32 val; 1291 }; 1292 1293 #define DLB2_CHP_LDB_CQ_DEPTH(x) \ 1294 (0x40900000 + (x) * 0x1000) 1295 #define DLB2_CHP_LDB_CQ_DEPTH_RST 0x0 1296 union dlb2_chp_ldb_cq_depth { 1297 struct { 1298 u32 depth : 11; 1299 u32 rsvd0 : 21; 1300 } field; 1301 u32 val; 1302 }; 1303 1304 #define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH(x) \ 1305 (0x40980000 + (x) * 0x1000) 1306 #define DLB2_CHP_LDB_CQ_INT_DEPTH_THRSH_RST 0x0 1307 union dlb2_chp_ldb_cq_int_depth_thrsh { 1308 struct { 1309 u32 depth_threshold : 11; 1310 u32 rsvd0 : 21; 1311 } field; 1312 u32 val; 1313 }; 1314 1315 #define DLB2_CHP_LDB_CQ_INT_ENB(x) \ 1316 (0x40a00000 + (x) * 0x1000) 1317 #define DLB2_CHP_LDB_CQ_INT_ENB_RST 0x0 1318 union dlb2_chp_ldb_cq_int_enb { 1319 struct { 1320 u32 en_tim : 1; 1321 u32 en_depth : 1; 1322 u32 rsvd0 : 30; 1323 } field; 1324 u32 val; 1325 }; 1326 1327 #define DLB2_CHP_LDB_CQ_TMR_THRSH(x) \ 1328 (0x40b00000 + (x) * 0x1000) 1329 #define DLB2_CHP_LDB_CQ_TMR_THRSH_RST 0x1 1330 union dlb2_chp_ldb_cq_tmr_thrsh { 1331 struct { 1332 u32 thrsh_0 : 1; 1333 u32 thrsh_13_1 : 13; 1334 u32 rsvd0 : 18; 1335 } field; 1336 u32 val; 1337 }; 1338 1339 #define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(x) \ 1340 (0x40b80000 + (x) * 0x1000) 1341 #define DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_RST 0x0 1342 union dlb2_chp_ldb_cq_tkn_depth_sel { 1343 struct { 1344 u32 token_depth_select : 4; 1345 u32 rsvd0 : 28; 1346 } field; 1347 u32 val; 1348 }; 1349 1350 #define DLB2_CHP_LDB_CQ_WD_ENB(x) \ 1351 (0x40c00000 + (x) * 0x1000) 1352 #define DLB2_CHP_LDB_CQ_WD_ENB_RST 0x0 1353 union dlb2_chp_ldb_cq_wd_enb { 1354 struct { 1355 u32 wd_enable : 1; 1356 u32 rsvd0 : 31; 1357 } field; 1358 u32 val; 1359 }; 1360 1361 #define DLB2_CHP_LDB_CQ_WPTR(x) \ 1362 (0x40c80000 + (x) * 0x1000) 1363 #define DLB2_CHP_LDB_CQ_WPTR_RST 0x0 1364 union dlb2_chp_ldb_cq_wptr { 1365 struct { 1366 u32 write_pointer : 11; 1367 u32 rsvd0 : 21; 1368 } field; 1369 u32 val; 1370 }; 1371 1372 #define DLB2_CHP_LDB_CQ2VAS(x) \ 1373 (0x40d00000 + (x) * 0x1000) 1374 #define DLB2_CHP_LDB_CQ2VAS_RST 0x0 1375 union dlb2_chp_ldb_cq2vas { 1376 struct { 1377 u32 cq2vas : 5; 1378 u32 rsvd0 : 27; 1379 } field; 1380 u32 val; 1381 }; 1382 1383 #define DLB2_CHP_CFG_CHP_CSR_CTRL 0x44000008 1384 #define DLB2_CHP_CFG_CHP_CSR_CTRL_RST 0x180002 1385 union dlb2_chp_cfg_chp_csr_ctrl { 1386 struct { 1387 u32 int_cor_alarm_dis : 1; 1388 u32 int_cor_synd_dis : 1; 1389 u32 int_uncr_alarm_dis : 1; 1390 u32 int_unc_synd_dis : 1; 1391 u32 int_inf0_alarm_dis : 1; 1392 u32 int_inf0_synd_dis : 1; 1393 u32 int_inf1_alarm_dis : 1; 1394 u32 int_inf1_synd_dis : 1; 1395 u32 int_inf2_alarm_dis : 1; 1396 u32 int_inf2_synd_dis : 1; 1397 u32 int_inf3_alarm_dis : 1; 1398 u32 int_inf3_synd_dis : 1; 1399 u32 int_inf4_alarm_dis : 1; 1400 u32 int_inf4_synd_dis : 1; 1401 u32 int_inf5_alarm_dis : 1; 1402 u32 int_inf5_synd_dis : 1; 1403 u32 dlb_cor_alarm_enable : 1; 1404 u32 cfg_64bytes_qe_ldb_cq_mode : 1; 1405 u32 cfg_64bytes_qe_dir_cq_mode : 1; 1406 u32 pad_write_ldb : 1; 1407 u32 pad_write_dir : 1; 1408 u32 pad_first_write_ldb : 1; 1409 u32 pad_first_write_dir : 1; 1410 u32 rsvz0 : 9; 1411 } field; 1412 u32 val; 1413 }; 1414 1415 #define DLB2_CHP_DIR_CQ_INTR_ARMED0 0x4400005c 1416 #define DLB2_CHP_DIR_CQ_INTR_ARMED0_RST 0x0 1417 union dlb2_chp_dir_cq_intr_armed0 { 1418 struct { 1419 u32 armed : 32; 1420 } field; 1421 u32 val; 1422 }; 1423 1424 #define DLB2_CHP_DIR_CQ_INTR_ARMED1 0x44000060 1425 #define DLB2_CHP_DIR_CQ_INTR_ARMED1_RST 0x0 1426 union dlb2_chp_dir_cq_intr_armed1 { 1427 struct { 1428 u32 armed : 32; 1429 } field; 1430 u32 val; 1431 }; 1432 1433 #define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL 0x44000084 1434 #define DLB2_CHP_CFG_DIR_CQ_TIMER_CTL_RST 0x0 1435 union dlb2_chp_cfg_dir_cq_timer_ctl { 1436 struct { 1437 u32 sample_interval : 8; 1438 u32 enb : 1; 1439 u32 rsvz0 : 23; 1440 } field; 1441 u32 val; 1442 }; 1443 1444 #define DLB2_CHP_CFG_DIR_WDTO_0 0x44000088 1445 #define DLB2_CHP_CFG_DIR_WDTO_0_RST 0x0 1446 union dlb2_chp_cfg_dir_wdto_0 { 1447 struct { 1448 u32 wdto : 32; 1449 } field; 1450 u32 val; 1451 }; 1452 1453 #define DLB2_CHP_CFG_DIR_WDTO_1 0x4400008c 1454 #define DLB2_CHP_CFG_DIR_WDTO_1_RST 0x0 1455 union dlb2_chp_cfg_dir_wdto_1 { 1456 struct { 1457 u32 wdto : 32; 1458 } field; 1459 u32 val; 1460 }; 1461 1462 #define DLB2_CHP_CFG_DIR_WD_DISABLE0 0x44000098 1463 #define DLB2_CHP_CFG_DIR_WD_DISABLE0_RST 0xffffffff 1464 union dlb2_chp_cfg_dir_wd_disable0 { 1465 struct { 1466 u32 wd_disable : 32; 1467 } field; 1468 u32 val; 1469 }; 1470 1471 #define DLB2_CHP_CFG_DIR_WD_DISABLE1 0x4400009c 1472 #define DLB2_CHP_CFG_DIR_WD_DISABLE1_RST 0xffffffff 1473 union dlb2_chp_cfg_dir_wd_disable1 { 1474 struct { 1475 u32 wd_disable : 32; 1476 } field; 1477 u32 val; 1478 }; 1479 1480 #define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL 0x440000a0 1481 #define DLB2_CHP_CFG_DIR_WD_ENB_INTERVAL_RST 0x0 1482 union dlb2_chp_cfg_dir_wd_enb_interval { 1483 struct { 1484 u32 sample_interval : 28; 1485 u32 enb : 1; 1486 u32 rsvz0 : 3; 1487 } field; 1488 u32 val; 1489 }; 1490 1491 #define DLB2_CHP_CFG_DIR_WD_THRESHOLD 0x440000ac 1492 #define DLB2_CHP_CFG_DIR_WD_THRESHOLD_RST 0x0 1493 union dlb2_chp_cfg_dir_wd_threshold { 1494 struct { 1495 u32 wd_threshold : 8; 1496 u32 rsvz0 : 24; 1497 } field; 1498 u32 val; 1499 }; 1500 1501 #define DLB2_CHP_LDB_CQ_INTR_ARMED0 0x440000b0 1502 #define DLB2_CHP_LDB_CQ_INTR_ARMED0_RST 0x0 1503 union dlb2_chp_ldb_cq_intr_armed0 { 1504 struct { 1505 u32 armed : 32; 1506 } field; 1507 u32 val; 1508 }; 1509 1510 #define DLB2_CHP_LDB_CQ_INTR_ARMED1 0x440000b4 1511 #define DLB2_CHP_LDB_CQ_INTR_ARMED1_RST 0x0 1512 union dlb2_chp_ldb_cq_intr_armed1 { 1513 struct { 1514 u32 armed : 32; 1515 } field; 1516 u32 val; 1517 }; 1518 1519 #define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL 0x440000d8 1520 #define DLB2_CHP_CFG_LDB_CQ_TIMER_CTL_RST 0x0 1521 union dlb2_chp_cfg_ldb_cq_timer_ctl { 1522 struct { 1523 u32 sample_interval : 8; 1524 u32 enb : 1; 1525 u32 rsvz0 : 23; 1526 } field; 1527 u32 val; 1528 }; 1529 1530 #define DLB2_CHP_CFG_LDB_WDTO_0 0x440000dc 1531 #define DLB2_CHP_CFG_LDB_WDTO_0_RST 0x0 1532 union dlb2_chp_cfg_ldb_wdto_0 { 1533 struct { 1534 u32 wdto : 32; 1535 } field; 1536 u32 val; 1537 }; 1538 1539 #define DLB2_CHP_CFG_LDB_WDTO_1 0x440000e0 1540 #define DLB2_CHP_CFG_LDB_WDTO_1_RST 0x0 1541 union dlb2_chp_cfg_ldb_wdto_1 { 1542 struct { 1543 u32 wdto : 32; 1544 } field; 1545 u32 val; 1546 }; 1547 1548 #define DLB2_CHP_CFG_LDB_WD_DISABLE0 0x440000ec 1549 #define DLB2_CHP_CFG_LDB_WD_DISABLE0_RST 0xffffffff 1550 union dlb2_chp_cfg_ldb_wd_disable0 { 1551 struct { 1552 u32 wd_disable : 32; 1553 } field; 1554 u32 val; 1555 }; 1556 1557 #define DLB2_CHP_CFG_LDB_WD_DISABLE1 0x440000f0 1558 #define DLB2_CHP_CFG_LDB_WD_DISABLE1_RST 0xffffffff 1559 union dlb2_chp_cfg_ldb_wd_disable1 { 1560 struct { 1561 u32 wd_disable : 32; 1562 } field; 1563 u32 val; 1564 }; 1565 1566 #define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL 0x440000f4 1567 #define DLB2_CHP_CFG_LDB_WD_ENB_INTERVAL_RST 0x0 1568 union dlb2_chp_cfg_ldb_wd_enb_interval { 1569 struct { 1570 u32 sample_interval : 28; 1571 u32 enb : 1; 1572 u32 rsvz0 : 3; 1573 } field; 1574 u32 val; 1575 }; 1576 1577 #define DLB2_CHP_CFG_LDB_WD_THRESHOLD 0x44000100 1578 #define DLB2_CHP_CFG_LDB_WD_THRESHOLD_RST 0x0 1579 union dlb2_chp_cfg_ldb_wd_threshold { 1580 struct { 1581 u32 wd_threshold : 8; 1582 u32 rsvz0 : 24; 1583 } field; 1584 u32 val; 1585 }; 1586 1587 #define DLB2_CHP_CTRL_DIAG_02 0x4c000028 1588 #define DLB2_CHP_CTRL_DIAG_02_RST 0x1555 1589 union dlb2_chp_ctrl_diag_02 { 1590 struct { 1591 u32 egress_credit_status_empty : 1; 1592 u32 egress_credit_status_afull : 1; 1593 u32 chp_outbound_hcw_pipe_credit_status_empty : 1; 1594 u32 chp_outbound_hcw_pipe_credit_status_afull : 1; 1595 u32 chp_lsp_ap_cmp_pipe_credit_status_empty : 1; 1596 u32 chp_lsp_ap_cmp_pipe_credit_status_afull : 1; 1597 u32 chp_lsp_tok_pipe_credit_status_empty : 1; 1598 u32 chp_lsp_tok_pipe_credit_status_afull : 1; 1599 u32 chp_rop_pipe_credit_status_empty : 1; 1600 u32 chp_rop_pipe_credit_status_afull : 1; 1601 u32 qed_to_cq_pipe_credit_status_empty : 1; 1602 u32 qed_to_cq_pipe_credit_status_afull : 1; 1603 u32 egress_lsp_token_credit_status_empty : 1; 1604 u32 egress_lsp_token_credit_status_afull : 1; 1605 u32 rsvd0 : 18; 1606 } field; 1607 u32 val; 1608 }; 1609 1610 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0 0x54000000 1611 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_0_RST 0xfefcfaf8 1612 union dlb2_dp_cfg_arb_weights_tqpri_dir_0 { 1613 struct { 1614 u32 pri0 : 8; 1615 u32 pri1 : 8; 1616 u32 pri2 : 8; 1617 u32 pri3 : 8; 1618 } field; 1619 u32 val; 1620 }; 1621 1622 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1 0x54000004 1623 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_DIR_1_RST 0x0 1624 union dlb2_dp_cfg_arb_weights_tqpri_dir_1 { 1625 struct { 1626 u32 rsvz0 : 32; 1627 } field; 1628 u32 val; 1629 }; 1630 1631 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x54000008 1632 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8 1633 union dlb2_dp_cfg_arb_weights_tqpri_replay_0 { 1634 struct { 1635 u32 pri0 : 8; 1636 u32 pri1 : 8; 1637 u32 pri2 : 8; 1638 u32 pri3 : 8; 1639 } field; 1640 u32 val; 1641 }; 1642 1643 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x5400000c 1644 #define DLB2_DP_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0 1645 union dlb2_dp_cfg_arb_weights_tqpri_replay_1 { 1646 struct { 1647 u32 rsvz0 : 32; 1648 } field; 1649 u32 val; 1650 }; 1651 1652 #define DLB2_DP_DIR_CSR_CTRL 0x54000010 1653 #define DLB2_DP_DIR_CSR_CTRL_RST 0x0 1654 union dlb2_dp_dir_csr_ctrl { 1655 struct { 1656 u32 int_cor_alarm_dis : 1; 1657 u32 int_cor_synd_dis : 1; 1658 u32 int_uncr_alarm_dis : 1; 1659 u32 int_unc_synd_dis : 1; 1660 u32 int_inf0_alarm_dis : 1; 1661 u32 int_inf0_synd_dis : 1; 1662 u32 int_inf1_alarm_dis : 1; 1663 u32 int_inf1_synd_dis : 1; 1664 u32 int_inf2_alarm_dis : 1; 1665 u32 int_inf2_synd_dis : 1; 1666 u32 int_inf3_alarm_dis : 1; 1667 u32 int_inf3_synd_dis : 1; 1668 u32 int_inf4_alarm_dis : 1; 1669 u32 int_inf4_synd_dis : 1; 1670 u32 int_inf5_alarm_dis : 1; 1671 u32 int_inf5_synd_dis : 1; 1672 u32 rsvz0 : 16; 1673 } field; 1674 u32 val; 1675 }; 1676 1677 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0 0x84000000 1678 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_0_RST 0xfefcfaf8 1679 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_0 { 1680 struct { 1681 u32 pri0 : 8; 1682 u32 pri1 : 8; 1683 u32 pri2 : 8; 1684 u32 pri3 : 8; 1685 } field; 1686 u32 val; 1687 }; 1688 1689 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1 0x84000004 1690 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_ATQ_1_RST 0x0 1691 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_atq_1 { 1692 struct { 1693 u32 rsvz0 : 32; 1694 } field; 1695 u32 val; 1696 }; 1697 1698 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0 0x84000008 1699 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_0_RST 0xfefcfaf8 1700 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_0 { 1701 struct { 1702 u32 pri0 : 8; 1703 u32 pri1 : 8; 1704 u32 pri2 : 8; 1705 u32 pri3 : 8; 1706 } field; 1707 u32 val; 1708 }; 1709 1710 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1 0x8400000c 1711 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_NALB_1_RST 0x0 1712 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_nalb_1 { 1713 struct { 1714 u32 rsvz0 : 32; 1715 } field; 1716 u32 val; 1717 }; 1718 1719 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0 0x84000010 1720 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_0_RST 0xfefcfaf8 1721 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_0 { 1722 struct { 1723 u32 pri0 : 8; 1724 u32 pri1 : 8; 1725 u32 pri2 : 8; 1726 u32 pri3 : 8; 1727 } field; 1728 u32 val; 1729 }; 1730 1731 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1 0x84000014 1732 #define DLB2_NALB_PIPE_CFG_ARB_WEIGHTS_TQPRI_REPLAY_1_RST 0x0 1733 union dlb2_nalb_pipe_cfg_arb_weights_tqpri_replay_1 { 1734 struct { 1735 u32 rsvz0 : 32; 1736 } field; 1737 u32 val; 1738 }; 1739 1740 #define DLB2_RO_PIPE_GRP_0_SLT_SHFT(x) \ 1741 (0x96000000 + (x) * 0x4) 1742 #define DLB2_RO_PIPE_GRP_0_SLT_SHFT_RST 0x0 1743 union dlb2_ro_pipe_grp_0_slt_shft { 1744 struct { 1745 u32 change : 10; 1746 u32 rsvd0 : 22; 1747 } field; 1748 u32 val; 1749 }; 1750 1751 #define DLB2_RO_PIPE_GRP_1_SLT_SHFT(x) \ 1752 (0x96010000 + (x) * 0x4) 1753 #define DLB2_RO_PIPE_GRP_1_SLT_SHFT_RST 0x0 1754 union dlb2_ro_pipe_grp_1_slt_shft { 1755 struct { 1756 u32 change : 10; 1757 u32 rsvd0 : 22; 1758 } field; 1759 u32 val; 1760 }; 1761 1762 #define DLB2_RO_PIPE_GRP_SN_MODE 0x94000000 1763 #define DLB2_RO_PIPE_GRP_SN_MODE_RST 0x0 1764 union dlb2_ro_pipe_grp_sn_mode { 1765 struct { 1766 u32 sn_mode_0 : 3; 1767 u32 rszv0 : 5; 1768 u32 sn_mode_1 : 3; 1769 u32 rszv1 : 21; 1770 } field; 1771 u32 val; 1772 }; 1773 1774 #define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0 0x9c000000 1775 #define DLB2_RO_PIPE_CFG_CTRL_GENERAL_0_RST 0x0 1776 union dlb2_ro_pipe_cfg_ctrl_general_0 { 1777 struct { 1778 u32 unit_single_step_mode : 1; 1779 u32 rr_en : 1; 1780 u32 rszv0 : 30; 1781 } field; 1782 u32 val; 1783 }; 1784 1785 #define DLB2_LSP_CQ2PRIOV(x) \ 1786 (0xa0000000 + (x) * 0x1000) 1787 #define DLB2_LSP_CQ2PRIOV_RST 0x0 1788 union dlb2_lsp_cq2priov { 1789 struct { 1790 u32 prio : 24; 1791 u32 v : 8; 1792 } field; 1793 u32 val; 1794 }; 1795 1796 #define DLB2_LSP_CQ2QID0(x) \ 1797 (0xa0080000 + (x) * 0x1000) 1798 #define DLB2_LSP_CQ2QID0_RST 0x0 1799 union dlb2_lsp_cq2qid0 { 1800 struct { 1801 u32 qid_p0 : 7; 1802 u32 rsvd3 : 1; 1803 u32 qid_p1 : 7; 1804 u32 rsvd2 : 1; 1805 u32 qid_p2 : 7; 1806 u32 rsvd1 : 1; 1807 u32 qid_p3 : 7; 1808 u32 rsvd0 : 1; 1809 } field; 1810 u32 val; 1811 }; 1812 1813 #define DLB2_LSP_CQ2QID1(x) \ 1814 (0xa0100000 + (x) * 0x1000) 1815 #define DLB2_LSP_CQ2QID1_RST 0x0 1816 union dlb2_lsp_cq2qid1 { 1817 struct { 1818 u32 qid_p4 : 7; 1819 u32 rsvd3 : 1; 1820 u32 qid_p5 : 7; 1821 u32 rsvd2 : 1; 1822 u32 qid_p6 : 7; 1823 u32 rsvd1 : 1; 1824 u32 qid_p7 : 7; 1825 u32 rsvd0 : 1; 1826 } field; 1827 u32 val; 1828 }; 1829 1830 #define DLB2_LSP_CQ_DIR_DSBL(x) \ 1831 (0xa0180000 + (x) * 0x1000) 1832 #define DLB2_LSP_CQ_DIR_DSBL_RST 0x1 1833 union dlb2_lsp_cq_dir_dsbl { 1834 struct { 1835 u32 disabled : 1; 1836 u32 rsvd0 : 31; 1837 } field; 1838 u32 val; 1839 }; 1840 1841 #define DLB2_LSP_CQ_DIR_TKN_CNT(x) \ 1842 (0xa0200000 + (x) * 0x1000) 1843 #define DLB2_LSP_CQ_DIR_TKN_CNT_RST 0x0 1844 union dlb2_lsp_cq_dir_tkn_cnt { 1845 struct { 1846 u32 count : 13; 1847 u32 rsvd0 : 19; 1848 } field; 1849 u32 val; 1850 }; 1851 1852 #define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(x) \ 1853 (0xa0280000 + (x) * 0x1000) 1854 #define DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI_RST 0x0 1855 union dlb2_lsp_cq_dir_tkn_depth_sel_dsi { 1856 struct { 1857 u32 token_depth_select : 4; 1858 u32 disable_wb_opt : 1; 1859 u32 ignore_depth : 1; 1860 u32 rsvd0 : 26; 1861 } field; 1862 u32 val; 1863 }; 1864 1865 #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL(x) \ 1866 (0xa0300000 + (x) * 0x1000) 1867 #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTL_RST 0x0 1868 union dlb2_lsp_cq_dir_tot_sch_cntl { 1869 struct { 1870 u32 count : 32; 1871 } field; 1872 u32 val; 1873 }; 1874 1875 #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH(x) \ 1876 (0xa0380000 + (x) * 0x1000) 1877 #define DLB2_LSP_CQ_DIR_TOT_SCH_CNTH_RST 0x0 1878 union dlb2_lsp_cq_dir_tot_sch_cnth { 1879 struct { 1880 u32 count : 32; 1881 } field; 1882 u32 val; 1883 }; 1884 1885 #define DLB2_LSP_CQ_LDB_DSBL(x) \ 1886 (0xa0400000 + (x) * 0x1000) 1887 #define DLB2_LSP_CQ_LDB_DSBL_RST 0x1 1888 union dlb2_lsp_cq_ldb_dsbl { 1889 struct { 1890 u32 disabled : 1; 1891 u32 rsvd0 : 31; 1892 } field; 1893 u32 val; 1894 }; 1895 1896 #define DLB2_LSP_CQ_LDB_INFL_CNT(x) \ 1897 (0xa0480000 + (x) * 0x1000) 1898 #define DLB2_LSP_CQ_LDB_INFL_CNT_RST 0x0 1899 union dlb2_lsp_cq_ldb_infl_cnt { 1900 struct { 1901 u32 count : 12; 1902 u32 rsvd0 : 20; 1903 } field; 1904 u32 val; 1905 }; 1906 1907 #define DLB2_LSP_CQ_LDB_INFL_LIM(x) \ 1908 (0xa0500000 + (x) * 0x1000) 1909 #define DLB2_LSP_CQ_LDB_INFL_LIM_RST 0x0 1910 union dlb2_lsp_cq_ldb_infl_lim { 1911 struct { 1912 u32 limit : 12; 1913 u32 rsvd0 : 20; 1914 } field; 1915 u32 val; 1916 }; 1917 1918 #define DLB2_LSP_CQ_LDB_TKN_CNT(x) \ 1919 (0xa0580000 + (x) * 0x1000) 1920 #define DLB2_LSP_CQ_LDB_TKN_CNT_RST 0x0 1921 union dlb2_lsp_cq_ldb_tkn_cnt { 1922 struct { 1923 u32 token_count : 11; 1924 u32 rsvd0 : 21; 1925 } field; 1926 u32 val; 1927 }; 1928 1929 #define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(x) \ 1930 (0xa0600000 + (x) * 0x1000) 1931 #define DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_RST 0x0 1932 union dlb2_lsp_cq_ldb_tkn_depth_sel { 1933 struct { 1934 u32 token_depth_select : 4; 1935 u32 ignore_depth : 1; 1936 u32 rsvd0 : 27; 1937 } field; 1938 u32 val; 1939 }; 1940 1941 #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL(x) \ 1942 (0xa0680000 + (x) * 0x1000) 1943 #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTL_RST 0x0 1944 union dlb2_lsp_cq_ldb_tot_sch_cntl { 1945 struct { 1946 u32 count : 32; 1947 } field; 1948 u32 val; 1949 }; 1950 1951 #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH(x) \ 1952 (0xa0700000 + (x) * 0x1000) 1953 #define DLB2_LSP_CQ_LDB_TOT_SCH_CNTH_RST 0x0 1954 union dlb2_lsp_cq_ldb_tot_sch_cnth { 1955 struct { 1956 u32 count : 32; 1957 } field; 1958 u32 val; 1959 }; 1960 1961 #define DLB2_LSP_QID_DIR_MAX_DEPTH(x) \ 1962 (0xa0780000 + (x) * 0x1000) 1963 #define DLB2_LSP_QID_DIR_MAX_DEPTH_RST 0x0 1964 union dlb2_lsp_qid_dir_max_depth { 1965 struct { 1966 u32 depth : 13; 1967 u32 rsvd0 : 19; 1968 } field; 1969 u32 val; 1970 }; 1971 1972 #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL(x) \ 1973 (0xa0800000 + (x) * 0x1000) 1974 #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTL_RST 0x0 1975 union dlb2_lsp_qid_dir_tot_enq_cntl { 1976 struct { 1977 u32 count : 32; 1978 } field; 1979 u32 val; 1980 }; 1981 1982 #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH(x) \ 1983 (0xa0880000 + (x) * 0x1000) 1984 #define DLB2_LSP_QID_DIR_TOT_ENQ_CNTH_RST 0x0 1985 union dlb2_lsp_qid_dir_tot_enq_cnth { 1986 struct { 1987 u32 count : 32; 1988 } field; 1989 u32 val; 1990 }; 1991 1992 #define DLB2_LSP_QID_DIR_ENQUEUE_CNT(x) \ 1993 (0xa0900000 + (x) * 0x1000) 1994 #define DLB2_LSP_QID_DIR_ENQUEUE_CNT_RST 0x0 1995 union dlb2_lsp_qid_dir_enqueue_cnt { 1996 struct { 1997 u32 count : 13; 1998 u32 rsvd0 : 19; 1999 } field; 2000 u32 val; 2001 }; 2002 2003 #define DLB2_LSP_QID_DIR_DEPTH_THRSH(x) \ 2004 (0xa0980000 + (x) * 0x1000) 2005 #define DLB2_LSP_QID_DIR_DEPTH_THRSH_RST 0x0 2006 union dlb2_lsp_qid_dir_depth_thrsh { 2007 struct { 2008 u32 thresh : 13; 2009 u32 rsvd0 : 19; 2010 } field; 2011 u32 val; 2012 }; 2013 2014 #define DLB2_LSP_QID_AQED_ACTIVE_CNT(x) \ 2015 (0xa0a00000 + (x) * 0x1000) 2016 #define DLB2_LSP_QID_AQED_ACTIVE_CNT_RST 0x0 2017 union dlb2_lsp_qid_aqed_active_cnt { 2018 struct { 2019 u32 count : 12; 2020 u32 rsvd0 : 20; 2021 } field; 2022 u32 val; 2023 }; 2024 2025 #define DLB2_LSP_QID_AQED_ACTIVE_LIM(x) \ 2026 (0xa0a80000 + (x) * 0x1000) 2027 #define DLB2_LSP_QID_AQED_ACTIVE_LIM_RST 0x0 2028 union dlb2_lsp_qid_aqed_active_lim { 2029 struct { 2030 u32 limit : 12; 2031 u32 rsvd0 : 20; 2032 } field; 2033 u32 val; 2034 }; 2035 2036 #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL(x) \ 2037 (0xa0b00000 + (x) * 0x1000) 2038 #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTL_RST 0x0 2039 union dlb2_lsp_qid_atm_tot_enq_cntl { 2040 struct { 2041 u32 count : 32; 2042 } field; 2043 u32 val; 2044 }; 2045 2046 #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH(x) \ 2047 (0xa0b80000 + (x) * 0x1000) 2048 #define DLB2_LSP_QID_ATM_TOT_ENQ_CNTH_RST 0x0 2049 union dlb2_lsp_qid_atm_tot_enq_cnth { 2050 struct { 2051 u32 count : 32; 2052 } field; 2053 u32 val; 2054 }; 2055 2056 #define DLB2_LSP_QID_ATQ_ENQUEUE_CNT(x) \ 2057 (0xa0c00000 + (x) * 0x1000) 2058 #define DLB2_LSP_QID_ATQ_ENQUEUE_CNT_RST 0x0 2059 union dlb2_lsp_qid_atq_enqueue_cnt { 2060 struct { 2061 u32 count : 14; 2062 u32 rsvd0 : 18; 2063 } field; 2064 u32 val; 2065 }; 2066 2067 #define DLB2_LSP_QID_LDB_ENQUEUE_CNT(x) \ 2068 (0xa0c80000 + (x) * 0x1000) 2069 #define DLB2_LSP_QID_LDB_ENQUEUE_CNT_RST 0x0 2070 union dlb2_lsp_qid_ldb_enqueue_cnt { 2071 struct { 2072 u32 count : 14; 2073 u32 rsvd0 : 18; 2074 } field; 2075 u32 val; 2076 }; 2077 2078 #define DLB2_LSP_QID_LDB_INFL_CNT(x) \ 2079 (0xa0d00000 + (x) * 0x1000) 2080 #define DLB2_LSP_QID_LDB_INFL_CNT_RST 0x0 2081 union dlb2_lsp_qid_ldb_infl_cnt { 2082 struct { 2083 u32 count : 12; 2084 u32 rsvd0 : 20; 2085 } field; 2086 u32 val; 2087 }; 2088 2089 #define DLB2_LSP_QID_LDB_INFL_LIM(x) \ 2090 (0xa0d80000 + (x) * 0x1000) 2091 #define DLB2_LSP_QID_LDB_INFL_LIM_RST 0x0 2092 union dlb2_lsp_qid_ldb_infl_lim { 2093 struct { 2094 u32 limit : 12; 2095 u32 rsvd0 : 20; 2096 } field; 2097 u32 val; 2098 }; 2099 2100 #define DLB2_LSP_QID2CQIDIX_00(x) \ 2101 (0xa0e00000 + (x) * 0x1000) 2102 #define DLB2_LSP_QID2CQIDIX_00_RST 0x0 2103 #define DLB2_LSP_QID2CQIDIX(x, y) \ 2104 (DLB2_LSP_QID2CQIDIX_00(x) + 0x80000 * (y)) 2105 #define DLB2_LSP_QID2CQIDIX_NUM 16 2106 union dlb2_lsp_qid2cqidix_00 { 2107 struct { 2108 u32 cq_p0 : 8; 2109 u32 cq_p1 : 8; 2110 u32 cq_p2 : 8; 2111 u32 cq_p3 : 8; 2112 } field; 2113 u32 val; 2114 }; 2115 2116 #define DLB2_LSP_QID2CQIDIX2_00(x) \ 2117 (0xa1600000 + (x) * 0x1000) 2118 #define DLB2_LSP_QID2CQIDIX2_00_RST 0x0 2119 #define DLB2_LSP_QID2CQIDIX2(x, y) \ 2120 (DLB2_LSP_QID2CQIDIX2_00(x) + 0x80000 * (y)) 2121 #define DLB2_LSP_QID2CQIDIX2_NUM 16 2122 union dlb2_lsp_qid2cqidix2_00 { 2123 struct { 2124 u32 cq_p0 : 8; 2125 u32 cq_p1 : 8; 2126 u32 cq_p2 : 8; 2127 u32 cq_p3 : 8; 2128 } field; 2129 u32 val; 2130 }; 2131 2132 #define DLB2_LSP_QID_LDB_REPLAY_CNT(x) \ 2133 (0xa1e00000 + (x) * 0x1000) 2134 #define DLB2_LSP_QID_LDB_REPLAY_CNT_RST 0x0 2135 union dlb2_lsp_qid_ldb_replay_cnt { 2136 struct { 2137 u32 count : 14; 2138 u32 rsvd0 : 18; 2139 } field; 2140 u32 val; 2141 }; 2142 2143 #define DLB2_LSP_QID_NALDB_MAX_DEPTH(x) \ 2144 (0xa1f00000 + (x) * 0x1000) 2145 #define DLB2_LSP_QID_NALDB_MAX_DEPTH_RST 0x0 2146 union dlb2_lsp_qid_naldb_max_depth { 2147 struct { 2148 u32 depth : 14; 2149 u32 rsvd0 : 18; 2150 } field; 2151 u32 val; 2152 }; 2153 2154 #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL(x) \ 2155 (0xa1f80000 + (x) * 0x1000) 2156 #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTL_RST 0x0 2157 union dlb2_lsp_qid_naldb_tot_enq_cntl { 2158 struct { 2159 u32 count : 32; 2160 } field; 2161 u32 val; 2162 }; 2163 2164 #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH(x) \ 2165 (0xa2000000 + (x) * 0x1000) 2166 #define DLB2_LSP_QID_NALDB_TOT_ENQ_CNTH_RST 0x0 2167 union dlb2_lsp_qid_naldb_tot_enq_cnth { 2168 struct { 2169 u32 count : 32; 2170 } field; 2171 u32 val; 2172 }; 2173 2174 #define DLB2_LSP_QID_ATM_DEPTH_THRSH(x) \ 2175 (0xa2080000 + (x) * 0x1000) 2176 #define DLB2_LSP_QID_ATM_DEPTH_THRSH_RST 0x0 2177 union dlb2_lsp_qid_atm_depth_thrsh { 2178 struct { 2179 u32 thresh : 14; 2180 u32 rsvd0 : 18; 2181 } field; 2182 u32 val; 2183 }; 2184 2185 #define DLB2_LSP_QID_NALDB_DEPTH_THRSH(x) \ 2186 (0xa2100000 + (x) * 0x1000) 2187 #define DLB2_LSP_QID_NALDB_DEPTH_THRSH_RST 0x0 2188 union dlb2_lsp_qid_naldb_depth_thrsh { 2189 struct { 2190 u32 thresh : 14; 2191 u32 rsvd0 : 18; 2192 } field; 2193 u32 val; 2194 }; 2195 2196 #define DLB2_LSP_QID_ATM_ACTIVE(x) \ 2197 (0xa2180000 + (x) * 0x1000) 2198 #define DLB2_LSP_QID_ATM_ACTIVE_RST 0x0 2199 union dlb2_lsp_qid_atm_active { 2200 struct { 2201 u32 count : 14; 2202 u32 rsvd0 : 18; 2203 } field; 2204 u32 val; 2205 }; 2206 2207 #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0 0xa4000008 2208 #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_0_RST 0x0 2209 union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_0 { 2210 struct { 2211 u32 pri0_weight : 8; 2212 u32 pri1_weight : 8; 2213 u32 pri2_weight : 8; 2214 u32 pri3_weight : 8; 2215 } field; 2216 u32 val; 2217 }; 2218 2219 #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1 0xa400000c 2220 #define DLB2_LSP_CFG_ARB_WEIGHT_ATM_NALB_QID_1_RST 0x0 2221 union dlb2_lsp_cfg_arb_weight_atm_nalb_qid_1 { 2222 struct { 2223 u32 rsvz0 : 32; 2224 } field; 2225 u32 val; 2226 }; 2227 2228 #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0 0xa4000014 2229 #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_0_RST 0x0 2230 union dlb2_lsp_cfg_arb_weight_ldb_qid_0 { 2231 struct { 2232 u32 pri0_weight : 8; 2233 u32 pri1_weight : 8; 2234 u32 pri2_weight : 8; 2235 u32 pri3_weight : 8; 2236 } field; 2237 u32 val; 2238 }; 2239 2240 #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1 0xa4000018 2241 #define DLB2_LSP_CFG_ARB_WEIGHT_LDB_QID_1_RST 0x0 2242 union dlb2_lsp_cfg_arb_weight_ldb_qid_1 { 2243 struct { 2244 u32 rsvz0 : 32; 2245 } field; 2246 u32 val; 2247 }; 2248 2249 #define DLB2_LSP_LDB_SCHED_CTRL 0xa400002c 2250 #define DLB2_LSP_LDB_SCHED_CTRL_RST 0x0 2251 union dlb2_lsp_ldb_sched_ctrl { 2252 struct { 2253 u32 cq : 8; 2254 u32 qidix : 3; 2255 u32 value : 1; 2256 u32 nalb_haswork_v : 1; 2257 u32 rlist_haswork_v : 1; 2258 u32 slist_haswork_v : 1; 2259 u32 inflight_ok_v : 1; 2260 u32 aqed_nfull_v : 1; 2261 u32 rsvz0 : 15; 2262 } field; 2263 u32 val; 2264 }; 2265 2266 #define DLB2_LSP_DIR_SCH_CNT_L 0xa4000034 2267 #define DLB2_LSP_DIR_SCH_CNT_L_RST 0x0 2268 union dlb2_lsp_dir_sch_cnt_l { 2269 struct { 2270 u32 count : 32; 2271 } field; 2272 u32 val; 2273 }; 2274 2275 #define DLB2_LSP_DIR_SCH_CNT_H 0xa4000038 2276 #define DLB2_LSP_DIR_SCH_CNT_H_RST 0x0 2277 union dlb2_lsp_dir_sch_cnt_h { 2278 struct { 2279 u32 count : 32; 2280 } field; 2281 u32 val; 2282 }; 2283 2284 #define DLB2_LSP_LDB_SCH_CNT_L 0xa400003c 2285 #define DLB2_LSP_LDB_SCH_CNT_L_RST 0x0 2286 union dlb2_lsp_ldb_sch_cnt_l { 2287 struct { 2288 u32 count : 32; 2289 } field; 2290 u32 val; 2291 }; 2292 2293 #define DLB2_LSP_LDB_SCH_CNT_H 0xa4000040 2294 #define DLB2_LSP_LDB_SCH_CNT_H_RST 0x0 2295 union dlb2_lsp_ldb_sch_cnt_h { 2296 struct { 2297 u32 count : 32; 2298 } field; 2299 u32 val; 2300 }; 2301 2302 #define DLB2_LSP_CFG_SHDW_CTRL 0xa4000070 2303 #define DLB2_LSP_CFG_SHDW_CTRL_RST 0x0 2304 union dlb2_lsp_cfg_shdw_ctrl { 2305 struct { 2306 u32 transfer : 1; 2307 u32 rsvd0 : 31; 2308 } field; 2309 u32 val; 2310 }; 2311 2312 #define DLB2_LSP_CFG_SHDW_RANGE_COS(x) \ 2313 (0xa4000074 + (x) * 4) 2314 #define DLB2_LSP_CFG_SHDW_RANGE_COS_RST 0x40 2315 union dlb2_lsp_cfg_shdw_range_cos { 2316 struct { 2317 u32 bw_range : 9; 2318 u32 rsvz0 : 22; 2319 u32 no_extra_credit : 1; 2320 } field; 2321 u32 val; 2322 }; 2323 2324 #define DLB2_LSP_CFG_CTRL_GENERAL_0 0xac000000 2325 #define DLB2_LSP_CFG_CTRL_GENERAL_0_RST 0x0 2326 union dlb2_lsp_cfg_ctrl_general_0 { 2327 struct { 2328 u32 disab_atq_empty_arb : 1; 2329 u32 inc_tok_unit_idle : 1; 2330 u32 disab_rlist_pri : 1; 2331 u32 inc_cmp_unit_idle : 1; 2332 u32 rsvz0 : 2; 2333 u32 dir_single_op : 1; 2334 u32 dir_half_bw : 1; 2335 u32 dir_single_out : 1; 2336 u32 dir_disab_multi : 1; 2337 u32 atq_single_op : 1; 2338 u32 atq_half_bw : 1; 2339 u32 atq_single_out : 1; 2340 u32 atq_disab_multi : 1; 2341 u32 dirrpl_single_op : 1; 2342 u32 dirrpl_half_bw : 1; 2343 u32 dirrpl_single_out : 1; 2344 u32 lbrpl_single_op : 1; 2345 u32 lbrpl_half_bw : 1; 2346 u32 lbrpl_single_out : 1; 2347 u32 ldb_single_op : 1; 2348 u32 ldb_half_bw : 1; 2349 u32 ldb_disab_multi : 1; 2350 u32 atm_single_sch : 1; 2351 u32 atm_single_cmp : 1; 2352 u32 ldb_ce_tog_arb : 1; 2353 u32 rsvz1 : 1; 2354 u32 smon0_valid_sel : 2; 2355 u32 smon0_value_sel : 1; 2356 u32 smon0_compare_sel : 2; 2357 } field; 2358 u32 val; 2359 }; 2360 2361 #define DLB2_CFG_MSTR_DIAG_RESET_STS 0xb4000000 2362 #define DLB2_CFG_MSTR_DIAG_RESET_STS_RST 0x80000bff 2363 union dlb2_cfg_mstr_diag_reset_sts { 2364 struct { 2365 u32 chp_pf_reset_done : 1; 2366 u32 rop_pf_reset_done : 1; 2367 u32 lsp_pf_reset_done : 1; 2368 u32 nalb_pf_reset_done : 1; 2369 u32 ap_pf_reset_done : 1; 2370 u32 dp_pf_reset_done : 1; 2371 u32 qed_pf_reset_done : 1; 2372 u32 dqed_pf_reset_done : 1; 2373 u32 aqed_pf_reset_done : 1; 2374 u32 sys_pf_reset_done : 1; 2375 u32 pf_reset_active : 1; 2376 u32 flrsm_state : 7; 2377 u32 rsvd0 : 13; 2378 u32 dlb_proc_reset_done : 1; 2379 } field; 2380 u32 val; 2381 }; 2382 2383 #define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS 0xb4000004 2384 #define DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS_RST 0x9d0fffff 2385 union dlb2_cfg_mstr_cfg_diagnostic_idle_status { 2386 struct { 2387 u32 chp_pipeidle : 1; 2388 u32 rop_pipeidle : 1; 2389 u32 lsp_pipeidle : 1; 2390 u32 nalb_pipeidle : 1; 2391 u32 ap_pipeidle : 1; 2392 u32 dp_pipeidle : 1; 2393 u32 qed_pipeidle : 1; 2394 u32 dqed_pipeidle : 1; 2395 u32 aqed_pipeidle : 1; 2396 u32 sys_pipeidle : 1; 2397 u32 chp_unit_idle : 1; 2398 u32 rop_unit_idle : 1; 2399 u32 lsp_unit_idle : 1; 2400 u32 nalb_unit_idle : 1; 2401 u32 ap_unit_idle : 1; 2402 u32 dp_unit_idle : 1; 2403 u32 qed_unit_idle : 1; 2404 u32 dqed_unit_idle : 1; 2405 u32 aqed_unit_idle : 1; 2406 u32 sys_unit_idle : 1; 2407 u32 rsvd1 : 4; 2408 u32 mstr_cfg_ring_idle : 1; 2409 u32 mstr_cfg_mstr_idle : 1; 2410 u32 mstr_flr_clkreq_b : 1; 2411 u32 mstr_proc_idle : 1; 2412 u32 mstr_proc_idle_masked : 1; 2413 u32 rsvd0 : 2; 2414 u32 dlb_func_idle : 1; 2415 } field; 2416 u32 val; 2417 }; 2418 2419 #define DLB2_CFG_MSTR_CFG_PM_STATUS 0xb4000014 2420 #define DLB2_CFG_MSTR_CFG_PM_STATUS_RST 0x100403e 2421 union dlb2_cfg_mstr_cfg_pm_status { 2422 struct { 2423 u32 prochot : 1; 2424 u32 pgcb_dlb_idle : 1; 2425 u32 pgcb_dlb_pg_rdy_ack_b : 1; 2426 u32 pmsm_pgcb_req_b : 1; 2427 u32 pgbc_pmc_pg_req_b : 1; 2428 u32 pmc_pgcb_pg_ack_b : 1; 2429 u32 pmc_pgcb_fet_en_b : 1; 2430 u32 pgcb_fet_en_b : 1; 2431 u32 rsvz0 : 1; 2432 u32 rsvz1 : 1; 2433 u32 fuse_force_on : 1; 2434 u32 fuse_proc_disable : 1; 2435 u32 rsvz2 : 1; 2436 u32 rsvz3 : 1; 2437 u32 pm_fsm_d0tod3_ok : 1; 2438 u32 pm_fsm_d3tod0_ok : 1; 2439 u32 dlb_in_d3 : 1; 2440 u32 rsvz4 : 7; 2441 u32 pmsm : 8; 2442 } field; 2443 u32 val; 2444 }; 2445 2446 #define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE 0xb4000018 2447 #define DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE_RST 0x1 2448 union dlb2_cfg_mstr_cfg_pm_pmcsr_disable { 2449 struct { 2450 u32 disable : 1; 2451 u32 rsvz0 : 31; 2452 } field; 2453 u32 val; 2454 }; 2455 2456 #define DLB2_FUNC_VF_VF2PF_MAILBOX_BYTES 256 2457 #define DLB2_FUNC_VF_VF2PF_MAILBOX(x) \ 2458 (0x1000 + (x) * 0x4) 2459 #define DLB2_FUNC_VF_VF2PF_MAILBOX_RST 0x0 2460 union dlb2_func_vf_vf2pf_mailbox { 2461 struct { 2462 u32 msg : 32; 2463 } field; 2464 u32 val; 2465 }; 2466 2467 #define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR 0x1f00 2468 #define DLB2_FUNC_VF_VF2PF_MAILBOX_ISR_RST 0x0 2469 #define DLB2_FUNC_VF_SIOV_VF2PF_MAILBOX_ISR_TRIGGER 0x8000 2470 union dlb2_func_vf_vf2pf_mailbox_isr { 2471 struct { 2472 u32 isr : 1; 2473 u32 rsvd0 : 31; 2474 } field; 2475 u32 val; 2476 }; 2477 2478 #define DLB2_FUNC_VF_PF2VF_MAILBOX_BYTES 64 2479 #define DLB2_FUNC_VF_PF2VF_MAILBOX(x) \ 2480 (0x2000 + (x) * 0x4) 2481 #define DLB2_FUNC_VF_PF2VF_MAILBOX_RST 0x0 2482 union dlb2_func_vf_pf2vf_mailbox { 2483 struct { 2484 u32 msg : 32; 2485 } field; 2486 u32 val; 2487 }; 2488 2489 #define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR 0x2f00 2490 #define DLB2_FUNC_VF_PF2VF_MAILBOX_ISR_RST 0x0 2491 union dlb2_func_vf_pf2vf_mailbox_isr { 2492 struct { 2493 u32 pf_isr : 1; 2494 u32 rsvd0 : 31; 2495 } field; 2496 u32 val; 2497 }; 2498 2499 #define DLB2_FUNC_VF_VF_MSI_ISR_PEND 0x2f10 2500 #define DLB2_FUNC_VF_VF_MSI_ISR_PEND_RST 0x0 2501 union dlb2_func_vf_vf_msi_isr_pend { 2502 struct { 2503 u32 isr_pend : 32; 2504 } field; 2505 u32 val; 2506 }; 2507 2508 #define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS 0x3000 2509 #define DLB2_FUNC_VF_VF_RESET_IN_PROGRESS_RST 0x1 2510 union dlb2_func_vf_vf_reset_in_progress { 2511 struct { 2512 u32 reset_in_progress : 1; 2513 u32 rsvd0 : 31; 2514 } field; 2515 u32 val; 2516 }; 2517 2518 #define DLB2_FUNC_VF_VF_MSI_ISR 0x4000 2519 #define DLB2_FUNC_VF_VF_MSI_ISR_RST 0x0 2520 union dlb2_func_vf_vf_msi_isr { 2521 struct { 2522 u32 vf_msi_isr : 32; 2523 } field; 2524 u32 val; 2525 }; 2526 2527 #endif /* __DLB2_REGS_H */ 2528