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Searched refs:set_masked (Results 1 – 2 of 2) sorted by relevance

/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c481 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) in set_masked() function
509 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in set_divisors()
510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
511 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
724 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pll_set_std()
725 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
726 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
911 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pllx_set_freq()
912 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
913 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c674 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) in set_masked() function
702 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); in set_divisors()
703 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
704 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
922 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
923 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
924 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
1145 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1182 reg = set_masked(reg, n, mnp_bits->n_shift, in pllx_set_freq()
1200 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()