Searched refs:rx_cfg (Results 1 – 3 of 3) sorted by relevance
811 uint32_t rx_cfg; in nlm_nae_init_ingress() local814 rx_cfg = nlm_read_nae_reg(nae_base, NAE_RX_CONFIG); in nlm_nae_init_ingress()815 rx_cfg &= ~(0x3 << 1); /* reset max message size */ in nlm_nae_init_ingress()816 rx_cfg &= ~(0xff << 4); /* clear freein desc cluster size */ in nlm_nae_init_ingress()817 rx_cfg &= ~(0x3f << 24); /* reset rx status mask */ /*XXX: why not 7f */ in nlm_nae_init_ingress()819 rx_cfg |= 1; /* rx enable */ in nlm_nae_init_ingress()820 rx_cfg |= (0x0 << 1); /* max message size */ in nlm_nae_init_ingress()821 rx_cfg |= (0x43 & 0x7f) << 24; /* rx status mask */ in nlm_nae_init_ingress()822 rx_cfg |= ((desc_size / 64) & 0xff) << 4; /* freein desc cluster size */ in nlm_nae_init_ingress()823 nlm_write_nae_reg(nae_base, NAE_RX_CONFIG, rx_cfg); in nlm_nae_init_ingress()
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */); in nix_lf_alloc()70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */); in nix_lf_alloc()71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */); in nix_lf_alloc()73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) | in nix_lf_alloc()
761 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ member