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Searched refs:rings (Results 1 – 25 of 52) sorted by relevance

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/f-stack/dpdk/drivers/event/octeontx/
H A Dtimvf_probe.c33 struct timvf_res rings[TIM_MAX_RINGS]; member
45 if (tdev.rings[i].domain != global_domain) in timvf_get_ring()
47 if (tdev.rings[i].in_use) in timvf_get_ring()
50 tdev.rings[i].in_use = true; in timvf_get_ring()
51 return tdev.rings[i].vfid; in timvf_get_ring()
64 if (tdev.rings[i].domain != global_domain) in timvf_release_ring()
66 if (tdev.rings[i].vfid == tim_ring_id) in timvf_release_ring()
67 tdev.rings[i].in_use = false; in timvf_release_ring()
84 if (tdev.rings[i].vfid == vfid) in timvf_bar()
85 res = &tdev.rings[i]; in timvf_bar()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.yaml49 ti,num-rings:
51 description: Number of rings supported by RA
53 ti,sci-rm-range-gp-rings:
75 - ti,num-rings
76 - ti,sci-rm-range-gp-rings
95 ti,num-rings = <818>;
96 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
H A Dk3-ringacc.txt25 - ti,num-rings : Number of rings supported by RA
26 - ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range
45 ti,num-rings = <818>;
46 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
/f-stack/freebsd/contrib/alpine-hal/
H A Dal_hal_udma_main.c179 al_reg_write32(&udma_q->q_regs->rings.drbp_low, in al_udma_q_set_pointers()
181 al_reg_write32(&udma_q->q_regs->rings.drbp_high, in al_udma_q_set_pointers()
184 al_reg_write32(&udma_q->q_regs->rings.drl, udma_q->size); in al_udma_q_set_pointers()
194 al_reg_write32(&udma_q->q_regs->rings.crbp_low, in al_udma_q_set_pointers()
196 al_reg_write32(&udma_q->q_regs->rings.crbp_high, in al_udma_q_set_pointers()
213 uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg); in al_udma_q_enable()
222 al_reg_write32(&udma_q->q_regs->rings.cfg, reg); in al_udma_q_enable()
384 status_reg = &udma_q->q_regs->rings.status; in al_udma_q_reset()
406 dcp_reg = &udma_q->q_regs->rings.dcp; in al_udma_q_reset()
407 crhp_reg = &udma_q->q_regs->rings.crhp; in al_udma_q_reset()
H A Dal_hal_udma_regs.h94 struct udma_rings_regs rings; member
H A Dal_hal_udma.h495 addr = &udma_q->q_regs->rings.drtp_inc; in al_udma_desc_action_add()
633 (al_reg_read32(&udma_q->q_regs->rings.crhp) & in al_udma_cdesc_get_all()
/f-stack/dpdk/doc/guides/eventdevs/
H A Docteontx2.rst33 - Up to 256 TIM rings aka event timer adapters.
34 - Up to 8 rings traversed in parallel.
111 - ``TIM limit max rings reserved``
114 rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW
116 rings.
123 When using multiple TIM rings the ``tim_ring_ctl`` devargs can be used to
124 control each TIM rings internal parameters uniquely. The following dict
H A Dsw.rst101 the events waiting in the ingress rings only once per call. The default
104 * ``deq_burst`` is the burst size used to dequeue from the port rings.
/f-stack/dpdk/doc/guides/nics/
H A Dmemif.rst79 message. Same behavior applies to rings. Client sends 'add ring' message
83 server maps regions to its address space, initializes rings and responds with
101 Regions contain rings and buffers. Rings and buffers can also be separated into multiple
102 regions. For no-zero-copy, rings and buffers are stored inside single memory
110 | S2M rings | M2S rings | packet buffer 0 | . | pb ((1 << pmd->run.log2_ring_size)*(s2m + m2s))-1 |
125 Descriptors are assigned packet buffers in order of rings creation. If we have one ring
187 Region 0 is created by memif driver and contains rings. Client interface exposes DPDK memory (memse…
196 | S2M rings | M2S rings |
H A Dpcap_ring.rst269 For the rings-based PMD, this functionality could be used, for example,
270 to allow data exchange between cores using rings to be done in exactly the
309 … one may want to have inter-core communication using pseudo Ethernet devices rather than raw rings,
312 … and dequeuing items from an rte_ring using the rings-based PMD may be slower than using the nativ…
/f-stack/dpdk/doc/guides/testpmd_app_ug/
H A Drun_app.rst89 Enable NUMA-aware allocation of RX/TX rings and of RX memory buffers
94 Disable NUMA-aware allocation of RX/TX rings and of RX memory buffers (mbufs).
102 Specify the socket on which the TX/RX rings for the port will be allocated.
271 Set the number of descriptors in the RX rings to N, where N > 0.
281 Set the number of descriptors in the TX rings to N, where N > 0.
309 Set the prefetch threshold register of RX rings to N, where N >= 0.
314 Set the host threshold register of RX rings to N, where N >= 0.
324 Set the write-back threshold register of RX rings to N, where N >= 0.
329 Set the prefetch threshold register of TX rings to N, where N >= 0.
334 Set the host threshold register of TX rings to N, where N >= 0.
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,wcnss.txt67 Definition: should reference the tx-enable and tx-rings-empty SMEM states
72 Definition: must contain "tx-enable" and "tx-rings-empty"
111 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
/f-stack/freebsd/contrib/device-tree/Bindings/net/
H A Dopencores-ethoc.txt6 first region is for the device registers and descriptor rings,
/f-stack/freebsd/contrib/device-tree/Bindings/crypto/
H A Dmediatek-crypto.txt7 order. These are global system and four descriptor rings.
H A Dbrcm,spu-crypto.txt15 Mailbox channels correspond to DMA rings on the device.
H A Dinside-secure-safexcel.txt8 - interrupts: Interrupt numbers for the rings and engine.
/f-stack/dpdk/doc/guides/sample_app_ug/
H A Dqos_scheduler.rst78 * A = Size (in number of buffer descriptors) of each of the NIC RX rings read
81 * B = Size (in number of elements) of each of the software rings used
84 * C = Size (in number of buffer descriptors) of each of the NIC TX rings written
91 * B = I/O RX lcore write burst size to the output software rings,
92 … worker lcore read burst size from input software rings,QoS enqueue size (the default value is 64)
H A Dmulti_process.rst130 Once the rings and memory pools are all available in both the primary and secondary processes,
231 giving the secondary process access to the hardware and software rings for each network port.
307 Instead, handles to all needed rings and memory pools are obtained via calls to rte_ring_lookup() a…
313 distributing those packets to the client queues (software rings, one for each client process) in ro…
314 On the client side, the packets are read from the rings in as big of bursts as possible, then route…
H A Dntb.rst63 Set the transmit free threshold of TX rings to N, where 0 <= N <=
/f-stack/freebsd/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-mcu.dtsi136 ti,num-rings = <286>;
137 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
H A Dk3-j721e-mcu-wakeup.dtsi269 ti,num-rings = <286>;
270 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
/f-stack/freebsd/contrib/device-tree/Bindings/rtc/
H A Disil,isl12057.txt13 RTC alarm rings. In order to mark the device has a wakeup source and
/f-stack/dpdk/doc/guides/cryptodevs/
H A Dmvsam.rst86 insmod crypto_safexcel.ko rings=0,0
/f-stack/freebsd/contrib/device-tree/Bindings/mailbox/
H A Dbrcm,iproc-flexrm-mbox.txt3 The Broadcom FlexRM ring manager provides a set of rings which can be
/f-stack/dpdk/doc/guides/prog_guide/
H A Doverview.rst24 Longest Prefix Match (LPM) and rings libraries are also provided.
34 a pipeline model may also be used by passing packets or messages between cores via the rings.

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