Searched refs:ring_ctrl_reg (Results 1 – 3 of 3) sorted by relevance
449 q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + in fpga_queue_setup()465 q->ring_ctrl_reg.ring_head_addr = in fpga_queue_setup()483 q->ring_ctrl_reg.ring_size = conf->queue_size; in fpga_queue_setup()487 q->ring_ctrl_reg.max_ul_dec = 0; in fpga_queue_setup()489 q->ring_ctrl_reg.max_ul_dec_en = 0; in fpga_queue_setup()492 q->ring_ctrl_reg.enable = 1; in fpga_queue_setup()495 q->ring_ctrl_reg.head_point = q->tail = 0; in fpga_queue_setup()498 q->ring_ctrl_reg.shadow_tail = q->tail; in fpga_queue_setup()505 fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg); in fpga_queue_setup()1587 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; in fpga_enqueue_ldpc_enc()[all …]
259 struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */ member
721 q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + in fpga_queue_setup()737 q->ring_ctrl_reg.ring_head_addr = in fpga_queue_setup()755 q->ring_ctrl_reg.ring_size = conf->queue_size; in fpga_queue_setup()759 q->ring_ctrl_reg.max_ul_dec = 0; in fpga_queue_setup()761 q->ring_ctrl_reg.max_ul_dec_en = 0; in fpga_queue_setup()764 q->ring_ctrl_reg.enable = 1; in fpga_queue_setup()767 q->ring_ctrl_reg.head_point = q->tail = 0; in fpga_queue_setup()770 q->ring_ctrl_reg.shadow_tail = q->tail; in fpga_queue_setup()777 fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg); in fpga_queue_setup()1957 q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; in fpga_enqueue_enc()[all …]