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Searched refs:reset_reg (Results 1 – 9 of 9) sorted by relevance

/f-stack/freebsd/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c891 uint32_t reg, mask, reset_reg; in tegra210_hwreset_by_idx() local
900 reset_reg = (reset) ? RST_DEV_Y_SET: RST_DEV_Y_CLR; in tegra210_hwreset_by_idx()
902 CLKDEV_WRITE_4(sc->dev, reset_reg, mask); in tegra210_hwreset_by_idx()
903 CLKDEV_READ_4(sc->dev, reset_reg, &reg); in tegra210_hwreset_by_idx()
906 reset_reg = get_reset_reg(idx); in tegra210_hwreset_by_idx()
908 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); in tegra210_hwreset_by_idx()
909 CLKDEV_READ_4(sc->dev, reset_reg, &reg); in tegra210_hwreset_by_idx()
/f-stack/freebsd/mips/atheros/
H A Dif_arge.c375 uint32_t reset_reg; in arge_reset_mac() local
389 reset_reg = RST_RESET_GE0_MAC; in arge_reset_mac()
391 reset_reg = RST_RESET_GE1_MAC; in arge_reset_mac()
402 reset_reg |= AR934X_RESET_GE0_MDIO; in arge_reset_mac()
404 reset_reg |= AR934X_RESET_GE1_MDIO; in arge_reset_mac()
411 reset_reg |= QCA955X_RESET_GE0_MDIO; in arge_reset_mac()
413 reset_reg |= QCA955X_RESET_GE1_MDIO; in arge_reset_mac()
420 reset_reg |= QCA953X_RESET_GE0_MDIO; in arge_reset_mac()
422 reset_reg |= QCA953X_RESET_GE1_MDIO; in arge_reset_mac()
426 ar71xx_device_stop(reset_reg); in arge_reset_mac()
[all …]
/f-stack/freebsd/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c777 uint32_t reg, mask, reset_reg; in tegra124_hwreset_by_idx() local
780 reset_reg = get_reset_reg(idx); in tegra124_hwreset_by_idx()
783 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); in tegra124_hwreset_by_idx()
784 CLKDEV_READ_4(sc->dev, reset_reg, &reg); in tegra124_hwreset_by_idx()
/f-stack/dpdk/drivers/net/qede/
H A Dqede_debug.c1393 const struct dbg_reset_reg *reset_reg; in qed_bus_reset_dbg_block() local
1397 reset_reg = qed_get_dbg_reset_reg(p_hwfn, block->reset_reg_id); in qed_bus_reset_dbg_block()
1399 DWORDS_TO_BYTES(GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR)); in qed_bus_reset_dbg_block()
1663 const struct dbg_reset_reg *reset_reg; in qed_grc_unreset_blocks() local
1666 reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id); in qed_grc_unreset_blocks()
1669 (reset_reg->data, DBG_RESET_REG_IS_REMOVED)) in qed_grc_unreset_blocks()
1674 GET_FIELD(reset_reg->data, in qed_grc_unreset_blocks()
2225 const struct dbg_reset_reg *reset_reg; in qed_grc_dump_reset_regs() local
2228 reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id); in qed_grc_dump_reset_regs()
2230 if (GET_FIELD(reset_reg->data, DBG_RESET_REG_IS_REMOVED)) in qed_grc_dump_reset_regs()
[all …]
/f-stack/dpdk/drivers/net/bnxt/
H A Dbnxt.h505 uint32_t reset_reg[BNXT_NUM_RESET_REG]; member
H A Dbnxt_hwrm.c5448 info->reset_reg[i] = in bnxt_hwrm_error_recovery_qcfg()
5449 rte_le_to_cpu_32(resp->reset_reg[i]); in bnxt_hwrm_error_recovery_qcfg()
H A Dbnxt_ethdev.c3631 uint32_t reg = info->reset_reg[index]; in bnxt_write_fw_reset_reg()
H A Dhsi_struct_def_dpdk.h16201 uint32_t reset_reg[16]; member
/f-stack/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c9239 uint32_t val, base_addr, offset, mask, reset_reg; in bnx2x_prev_unload_close_mac() local
9250 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); in bnx2x_prev_unload_close_mac()
9255 if ((mask & reset_reg) && val) { in bnx2x_prev_unload_close_mac()
9282 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { in bnx2x_prev_unload_close_mac()
9296 if (mask & reset_reg) { in bnx2x_prev_unload_close_mac()
9330 uint32_t reset_reg, tmp_reg = 0, rc; in bnx2x_prev_unload_common() local
9347 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); in bnx2x_prev_unload_common()
9350 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { in bnx2x_prev_unload_common()
9361 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { in bnx2x_prev_unload_common()