Home
last modified time | relevance | path

Searched refs:regval (Results 1 – 25 of 41) sorted by relevance

12

/f-stack/freebsd/amd64/amd64/
H A Dgdb_machdep.c95 register_t regval = *(register_t *)val; in gdb_cpu_setreg() local
103 case GDB_REG_RAX: kdb_frame->tf_rax = regval; break; in gdb_cpu_setreg()
104 case GDB_REG_RBX: kdb_frame->tf_rbx = regval; break; in gdb_cpu_setreg()
105 case GDB_REG_RCX: kdb_frame->tf_rcx = regval; break; in gdb_cpu_setreg()
106 case GDB_REG_RDX: kdb_frame->tf_rdx = regval; break; in gdb_cpu_setreg()
107 case GDB_REG_RSI: kdb_frame->tf_rsi = regval; break; in gdb_cpu_setreg()
108 case GDB_REG_RDI: kdb_frame->tf_rdi = regval; break; in gdb_cpu_setreg()
109 case GDB_REG_RBP: kdb_frame->tf_rbp = regval; break; in gdb_cpu_setreg()
110 case GDB_REG_RSP: kdb_frame->tf_rsp = regval; break; in gdb_cpu_setreg()
111 case GDB_REG_R8: kdb_frame->tf_r8 = regval; break; in gdb_cpu_setreg()
[all …]
/f-stack/freebsd/arm64/arm64/
H A Dgdb_machdep.c75 register_t regval = *(register_t *)val; in gdb_cpu_setreg() local
80 case GDB_REG_PC: kdb_frame->tf_elr = regval; break; in gdb_cpu_setreg()
81 case GDB_REG_SP: kdb_frame->tf_sp = regval; break; in gdb_cpu_setreg()
84 kdb_frame->tf_x[regnum] = regval; in gdb_cpu_setreg()
91 case GDB_REG_LR: kdb_thrctx->pcb_lr = regval; break; in gdb_cpu_setreg()
92 case GDB_REG_SP: kdb_thrctx->pcb_sp = regval; break; in gdb_cpu_setreg()
95 kdb_thrctx->pcb_x[regnum] = regval; in gdb_cpu_setreg()
/f-stack/freebsd/arm/freescale/imx/
H A Dimx51_ccm.c553 uint32_t regval; in imx_ccm_usb_enable() local
559 regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); in imx_ccm_usb_enable()
560 regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; in imx_ccm_usb_enable()
561 regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; in imx_ccm_usb_enable()
562 ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); in imx_ccm_usb_enable()
567 regval = ccm_read_4(ccm_softc, CCMC_CSCDR1); in imx_ccm_usb_enable()
568 regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; in imx_ccm_usb_enable()
569 regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; in imx_ccm_usb_enable()
570 regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; in imx_ccm_usb_enable()
571 regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; in imx_ccm_usb_enable()
[all …]
/f-stack/freebsd/mips/nlm/dev/net/
H A Dxaui.c52 uint32_t regval; in nlm_xaui_pcs_init() local
123 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
124 } while ((regval & LANE_TX_CLK) == 0); in nlm_xaui_pcs_init()
128 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
129 } while ((regval & LANE_RX_CLK) == 0); in nlm_xaui_pcs_init()
133 regval = nlm_read_nae_reg(nae_base, reg); in nlm_xaui_pcs_init()
134 } while ((regval & XAUI_LANE_FAULT) != 0); in nlm_xaui_pcs_init()
/f-stack/dpdk/drivers/net/octeontx2/
H A Dotx2_tm.c288 req->regval[2] = 0; in populate_tm_tl1_default()
398 regval[k] = (adjust | in prepare_tm_shaper_reg()
417 regval[k] = (adjust | in prepare_tm_shaper_reg()
436 regval[k] = (adjust | in prepare_tm_shaper_reg()
456 regval[k] = (adjust | in prepare_tm_shaper_reg()
471 regval[k] = (adjust | in prepare_tm_shaper_reg()
492 regval[k] = enable; in prepare_tm_sw_xoff()
675 otx2_mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k); in populate_tm_reg()
886 req->regval); in nix_clear_path_xoff()
1741 *regval = rsp->regval[0]; in read_tm_reg()
[all …]
/f-stack/freebsd/arm/ti/am335x/
H A Dam335x_ehrpwm.c223 uint16_t regval; in am335x_ehrpwm_cfg_enable() local
232 regval = EPWM_READ2(sc, EPWM_AQCSFRC); in am335x_ehrpwm_cfg_enable()
233 regval &= ~AQCSFRC(chan, AQCSFRC_MASK); in am335x_ehrpwm_cfg_enable()
236 regval |= AQCSFRC(chan, AQCSFRC_HI); in am335x_ehrpwm_cfg_enable()
238 regval |= AQCSFRC(chan, AQCSFRC_LO); in am335x_ehrpwm_cfg_enable()
240 EPWM_WRITE2(sc, EPWM_AQCSFRC, regval); in am335x_ehrpwm_cfg_enable()
246 uint16_t regval; in am335x_ehrpwm_cfg_period() local
292 regval = EPWM_READ2(sc, EPWM_TBCTL); in am335x_ehrpwm_cfg_period()
293 regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK); in am335x_ehrpwm_cfg_period()
294 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv); in am335x_ehrpwm_cfg_period()
[all …]
/f-stack/freebsd/arm64/cavium/
H A Dthunder_pcie_pem.c455 uint64_t regval; in thunder_pem_slix_s2m_regx_acc_modify() local
469 regval = bus_space_read_8(sc->reg_bst, handle, in thunder_pem_slix_s2m_regx_acc_modify()
471 regval &= ~(0xFFFFFFFFUL); in thunder_pem_slix_s2m_regx_acc_modify()
473 PEM_CFG_SLIX_TO_REG(slix), regval); in thunder_pem_slix_s2m_regx_acc_modify()
480 uint64_t regval; in thunder_pem_link_init() local
483 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); in thunder_pem_link_init()
484 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { in thunder_pem_link_init()
489 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); in thunder_pem_link_init()
490 regval |= PEM_LINK_ENABLE; in thunder_pem_link_init()
496 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); in thunder_pem_link_init()
[all …]
/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_mci.c934 uint32_t regval; in ar9300_mci_set_btcoex_ctrl_9565_1ANT() local
949 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval); in ar9300_mci_set_btcoex_ctrl_9565_1ANT()
954 uint32_t regval; in ar9300_mci_set_btcoex_ctrl_9565_2ANT() local
969 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval); in ar9300_mci_set_btcoex_ctrl_9565_2ANT()
974 uint32_t regval; in ar9300_mci_set_btcoex_ctrl_9462() local
991 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval); in ar9300_mci_set_btcoex_ctrl_9462()
999 u_int32_t regval; in ar9300_mci_reset() local
1138 regval = OS_REG_READ(ah, AR_MCI_COMMAND2); in ar9300_mci_reset()
1289 u_int32_t regval; in ar9300_mci_send_message() local
1292 regval = OS_REG_READ(ah, AR_BTCOEX_CTRL); in ar9300_mci_send_message()
[all …]
H A Dar9300_eeprom.c1638 u_int32_t regval; in ar9300_ant_ctrl_apply() local
1743 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9300_ant_ctrl_apply()
1748 regval |= ((value >> 6) & 0x1) << in ar9300_ant_ctrl_apply()
1752 regval |= ANT_DIV_ENABLE; in ar9300_ant_ctrl_apply()
1778 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9300_ant_ctrl_apply()
1781 regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT); in ar9300_ant_ctrl_apply()
1783 regval |= ((value >> 7) & 0x1) << in ar9300_ant_ctrl_apply()
1788 regval |= FAST_DIV_ENABLE; in ar9300_ant_ctrl_apply()
1804 regval |= (HAL_ANT_DIV_COMB_LNA1 << in ar9300_ant_ctrl_apply()
1806 regval |= (HAL_ANT_DIV_COMB_LNA2 << in ar9300_ant_ctrl_apply()
[all …]
H A Dar9300_reset.c133 u_int32_t tx_lat, rx_lat, usec, slot, regval, eifs; in ar9300_set_ifs_timing() local
135 regval = OS_REG_READ(ah, AR_USEC); in ar9300_set_ifs_timing()
4051 u_int32_t regval; in ar9300_set_dma() local
4060 regval = OS_REG_READ(ah, AR_AHB_MODE); in ar9300_set_dma()
6446 u_int32_t regval; in ar9300_ant_ctrl_set_lna_div_use_bt_ant() local
6489 regval |= ((value >> 6) & 0x1) << in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6492 regval |= ANT_DIV_ENABLE; in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6499 regval |= ((value >> 7) & 0x1) << in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6502 regval |= FAST_DIV_ENABLE; in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
6544 regval |= (HAL_ANT_DIV_COMB_LNA1 << in ar9300_ant_ctrl_set_lna_div_use_bt_ant()
[all …]
/f-stack/freebsd/mips/mediatek/
H A Dmtk_gpio_v2.c176 uint32_t regval, mask = (1u << pin); in mtk_gpio_pin_set_direction() local
181 regval = MTK_READ_4(sc, GPIO_PIODIR(sc)); in mtk_gpio_pin_set_direction()
183 regval &= ~mask; in mtk_gpio_pin_set_direction()
185 regval |= mask; in mtk_gpio_pin_set_direction()
186 MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval); in mtk_gpio_pin_set_direction()
197 uint32_t regval, mask = (1u << pin); in mtk_gpio_pin_set_invert() local
199 regval = MTK_READ_4(sc, GPIO_PIOPOL(sc)); in mtk_gpio_pin_set_invert()
201 regval |= mask; in mtk_gpio_pin_set_invert()
203 regval &= ~mask; in mtk_gpio_pin_set_invert()
204 MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval); in mtk_gpio_pin_set_invert()
H A Dmtk_gpio_v1.c185 uint32_t regval, mask = (1u << pin); in mtk_gpio_pin_set_direction() local
190 regval = MTK_READ_4(sc, GPIO_PIODIR); in mtk_gpio_pin_set_direction()
192 regval &= ~mask; in mtk_gpio_pin_set_direction()
194 regval |= mask; in mtk_gpio_pin_set_direction()
195 MTK_WRITE_4(sc, GPIO_PIODIR, regval); in mtk_gpio_pin_set_direction()
206 uint32_t regval, mask = (1u << pin); in mtk_gpio_pin_set_invert() local
208 regval = MTK_READ_4(sc, GPIO_PIOPOL); in mtk_gpio_pin_set_invert()
210 regval |= mask; in mtk_gpio_pin_set_invert()
212 regval &= ~mask; in mtk_gpio_pin_set_invert()
213 MTK_WRITE_4(sc, GPIO_PIOPOL, regval); in mtk_gpio_pin_set_invert()
/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_82598.c226 u32 regval; in ixgbe_start_hw_82598() local
239 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); in ixgbe_start_hw_82598()
240 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_82598()
241 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); in ixgbe_start_hw_82598()
246 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_82598()
247 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_82598()
249 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_82598()
1334 u32 regval; in ixgbe_enable_relaxed_ordering_82598() local
1343 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_enable_relaxed_ordering_82598()
1350 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_82598()
[all …]
H A Dixgbe_82598.h23 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_82599.h32 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_common.c423 u32 regval; in ixgbe_start_hw_gen2() local
435 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_gen2()
440 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
441 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_gen2()
443 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
3409 if (regval & IXGBE_RXCTRL_RXEN) in ixgbe_enable_rx_dma_generic()
4411 u32 regval; in ixgbe_enable_relaxed_ordering_gen2() local
4419 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_enable_relaxed_ordering_gen2()
4424 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_enable_relaxed_ordering_gen2()
4425 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_enable_relaxed_ordering_gen2()
[all …]
/f-stack/app/redis-5.0.5/src/
H A Dhyperloglog.c587 int idx = 0, runlen, regval; in hllSparseToDense() local
616 regval = HLL_SPARSE_VAL_VALUE(p); in hllSparseToDense()
619 HLL_DENSE_SET_REGISTER(hdr->registers,idx,regval); in hllSparseToDense()
912 int idx = 0, runlen, regval; in hllSparseRegHisto() local
928 regval = HLL_SPARSE_VAL_VALUE(p); in hllSparseRegHisto()
930 reghisto[regval] += runlen; in hllSparseRegHisto()
1081 long runlen, regval; in hllMerge() local
1096 regval = HLL_SPARSE_VAL_VALUE(p); in hllMerge()
1099 if (regval > max[i]) max[i] = regval; in hllMerge()
1544 int runlen, regval; in pfdebugCommand() local
[all …]
/f-stack/freebsd/arm/ti/
H A Dti_sdhci.c421 uint32_t regval; in ti_sdhci_hw_init() local
497 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); in ti_sdhci_hw_init()
499 regval |= MMCHS_SD_CAPA_VS18; in ti_sdhci_hw_init()
501 regval |= MMCHS_SD_CAPA_VS30; in ti_sdhci_hw_init()
502 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); in ti_sdhci_hw_init()
/f-stack/freebsd/mips/nlm/dev/sec/
H A Dnlmrsa.c140 uint32_t fbvc, dstvc, endsel, regval; in xlp_rsa_init() local
193 regval = 0xFFFF; in xlp_rsa_init()
196 regval = 0x07FFFFFF; in xlp_rsa_init()
199 nlm_write_rsa_reg(base, RSA_ENG_SEL_0 + i, regval); in xlp_rsa_init()
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_ich8lan.c133 u16 regval; member
146 u16 regval; member
157 u16 regval; member
3632 hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3659 hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
4386 hsflctl.regval = in e1000_write_flash_data_ich8lan()
4389 hsflctl.regval = in e1000_write_flash_data_ich8lan()
4404 hsflctl.regval); in e1000_write_flash_data_ich8lan()
4497 hsflctl.regval); in e1000_write_flash_data32_ich8lan()
4695 hsflctl.regval = in e1000_erase_flash_bank_ich8lan()
[all …]
/f-stack/freebsd/amd64/vmm/intel/
H A Dvmx.c1774 vmxctx->guest_rax = regval; in vmx_set_guest_reg()
1777 vmxctx->guest_rcx = regval; in vmx_set_guest_reg()
1780 vmxctx->guest_rdx = regval; in vmx_set_guest_reg()
1783 vmxctx->guest_rbx = regval; in vmx_set_guest_reg()
1789 vmxctx->guest_rbp = regval; in vmx_set_guest_reg()
1792 vmxctx->guest_rsi = regval; in vmx_set_guest_reg()
1798 vmxctx->guest_r8 = regval; in vmx_set_guest_reg()
1801 vmxctx->guest_r9 = regval; in vmx_set_guest_reg()
1829 uint64_t crval, regval; in vmx_emulate_cr0_access() local
1843 if (regval & CR0_PG) { in vmx_emulate_cr0_access()
[all …]
/f-stack/dpdk/drivers/net/bnxt/tf_ulp/
H A Dulp_mapper.c41 uint64_t *regval) in ulp_mapper_glb_resource_read() argument
43 if (!mapper_data || !regval || in ulp_mapper_glb_resource_read()
61 uint64_t regval) in ulp_mapper_glb_resource_write() argument
74 ent->resource_hndl = regval; in ulp_mapper_glb_resource_write()
90 uint64_t regval; in ulp_mapper_resource_ident_allocate() local
111 regval = tfp_cpu_to_be_64((uint64_t)iparms.id); in ulp_mapper_resource_ident_allocate()
138 uint64_t regval; in ulp_mapper_resource_index_tbl_alloc() local
785 uint64_t regval; in ulp_mapper_result_field_process() local
906 idx, &regval)) { in ulp_mapper_result_field_process()
2165 uint64_t regval; in ulp_mapper_cache_tbl_process() local
[all …]
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_nvm.h55 u32 regval; /* Storage for register value */ member
H A Dice_nvm.c1030 cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval)) in ice_validate_nvm_rw_reg()
1089 data->regval = rd32(hw, cmd->offset); in ice_nvm_access_read()
1125 cmd->offset, data->regval); in ice_nvm_access_write()
1128 wr32(hw, cmd->offset, data->regval); in ice_nvm_access_write()
/f-stack/freebsd/amd64/vmm/
H A Dvmm_dev.c321 uint64_t *regval) in vm_get_register_set() argument
327 error = vm_get_register(vm, vcpu, regnum[i], &regval[i]); in vm_get_register_set()
336 uint64_t *regval) in vm_set_register_set() argument
342 error = vm_set_register(vm, vcpu, regnum[i], regval[i]); in vm_set_register_set()
669 &vmreg->regval); in vmmdev_ioctl()
674 vmreg->regval); in vmmdev_ioctl()

12