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Searched refs:reg_offset (Results 1 – 22 of 22) sorted by relevance

/f-stack/freebsd/arm/ti/clk/
H A Dti_clkctrl.c98 create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset,
123 uint32_t index, reg_offset, reg_address; in ti_clkctrl_attach() local
198 for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) { in ti_clkctrl_attach()
199 err = create_clkctrl(sc, reg, index, reg_offset, parent_offset, in ti_clkctrl_attach()
209 reg_address = reg[index] + reg_offset-reg[0]; in ti_clkctrl_attach()
214 err = create_clkctrl(sc, reg, index, reg_offset, in ti_clkctrl_attach()
221 reg_address = reg[index] + reg_offset - reg[0]; in ti_clkctrl_attach()
224 err = create_clkctrl(sc, reg, index, reg_offset, in ti_clkctrl_attach()
303 def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg; in create_clkctrl()
304 def.register_offset = parent_offset + reg[index] + reg_offset; in create_clkctrl()
[all …]
/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_regs.c255 uint32_t reg_offset; in hns3_direct_access_regs() local
284 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_direct_access_regs()
287 ring_reg_addrs[i] + reg_offset); in hns3_direct_access_regs()
295 reg_offset = HNS3_TQP_INTR_REG_SIZE * j; in hns3_direct_access_regs()
299 reg_offset); in hns3_direct_access_regs()
H A Dhns3_stats.c658 uint32_t reg_offset; in hns3_get_queue_stats() local
664 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_get_queue_stats()
666 reg_offset + hns3_rx_queue_strings[i].offset); in hns3_get_queue_stats()
675 reg_offset = hns3_get_tqp_reg_offset(j); in hns3_get_queue_stats()
677 reg_offset + hns3_tx_queue_strings[i].offset); in hns3_get_queue_stats()
H A Dhns3_rxtx.c359 uint32_t reg_offset; in hns3_stop_unused_queue() local
362 reg_offset = queue_type == HNS3_RING_TYPE_TX ? in hns3_stop_unused_queue()
364 reg = hns3_read_reg(tqp_base, reg_offset); in hns3_stop_unused_queue()
366 hns3_write_reg(tqp_base, reg_offset, reg); in hns3_stop_unused_queue()
1696 uint32_t reg_offset; in hns3_get_tqp_reg_offset() local
1700 reg_offset = HNS3_TQP_REG_OFFSET + queue_id * HNS3_TQP_REG_SIZE; in hns3_get_tqp_reg_offset()
1702 reg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_EXT_REG_OFFSET + in hns3_get_tqp_reg_offset()
1706 return reg_offset; in hns3_get_tqp_reg_offset()
/f-stack/dpdk/drivers/net/qede/base/
H A Decore_init_fw_funcs.c1118 u32 ctrl, inc_val, reg_offset; in ecore_init_nig_lb_rl() local
1170 tc++, reg_offset += 4) { in ecore_init_nig_lb_rl()
1187 reg_offset, inc_val); in ecore_init_nig_lb_rl()
1195 reg_offset, ctrl); in ecore_init_nig_lb_rl()
1381 reg_offset, full_xoff_th); in ecore_init_brb_ram()
1384 reg_offset, full_xon_th); in ecore_init_brb_ram()
1387 reg_offset, pause_xoff_th); in ecore_init_brb_ram()
1390 reg_offset, pause_xon_th); in ecore_init_brb_ram()
1397 reg_offset, full_xoff_th); in ecore_init_brb_ram()
1400 reg_offset, full_xon_th); in ecore_init_brb_ram()
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H A Decore_cxt.c1998 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; in ecore_cxt_dynamic_ilt_alloc() local
2069 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_dynamic_ilt_alloc()
2081 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), in ecore_cxt_dynamic_ilt_alloc()
2101 u32 reg_offset, elem_size, hw_p_size, elems_per_p; in ecore_cxt_free_ilt_range() local
2163 reg_offset = PSWRQ2_REG_ILT_MEMORY + in ecore_cxt_free_ilt_range()
2172 reg_offset, in ecore_cxt_free_ilt_range()
H A Decore_hsi_debug_tools.h564 u16 reg_offset; member
/f-stack/dpdk/drivers/crypto/ccp/
H A Dccp_dev.h166 #define CCP_READ_REG(hw_addr, reg_offset) \ argument
167 ccp_pci_reg_read(hw_addr, reg_offset)
169 #define CCP_WRITE_REG(hw_addr, reg_offset, value) \ argument
170 ccp_pci_reg_write(hw_addr, reg_offset, value)
/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_mbx.c191 u32 reg_offset = (vf_number < 32) ? 0 : 1; in txgbe_check_for_rst_pf() local
198 vflre = rd32(hw, TXGBE_FLRVFE(reg_offset)); in txgbe_check_for_rst_pf()
201 wr32(hw, TXGBE_FLRVFEC(reg_offset), (1 << vf_shift)); in txgbe_check_for_rst_pf()
/f-stack/dpdk/drivers/net/ixgbe/
H A Dixgbe_pf.c384 uint32_t reg_offset, vf_shift; in ixgbe_vf_reset_msg() local
391 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; in ixgbe_vf_reset_msg()
394 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); in ixgbe_vf_reset_msg()
396 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); in ixgbe_vf_reset_msg()
408 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); in ixgbe_vf_reset_msg()
410 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); in ixgbe_vf_reset_msg()
413 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); in ixgbe_vf_reset_msg()
415 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); in ixgbe_vf_reset_msg()
/f-stack/dpdk/drivers/net/txgbe/
H A Dtxgbe_pf.c374 uint32_t reg_offset, vf_shift; in txgbe_vf_reset_msg() local
381 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; in txgbe_vf_reset_msg()
384 reg = rd32(hw, TXGBE_POOLTXENA(reg_offset)); in txgbe_vf_reset_msg()
386 wr32(hw, TXGBE_POOLTXENA(reg_offset), reg); in txgbe_vf_reset_msg()
397 reg = rd32(hw, TXGBE_POOLRXENA(reg_offset)); in txgbe_vf_reset_msg()
399 wr32(hw, TXGBE_POOLRXENA(reg_offset), reg); in txgbe_vf_reset_msg()
/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_mbx.c567 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
576 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
582 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
590 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
/f-stack/dpdk/drivers/crypto/octeontx2/
H A Dotx2_cryptodev_mbox.c167 msg->reg_offset = reg; in otx2_cpt_af_reg_read()
203 msg->reg_offset = reg; in otx2_cpt_af_reg_write()
/f-stack/freebsd/contrib/alpine-hal/
H A Dal_hal_pcie.h955 unsigned int reg_offset);
971 unsigned int reg_offset,
H A Dal_hal_pcie.c2249 unsigned int reg_offset) in al_pcie_local_cfg_space_read() argument
2254 data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]); in al_pcie_local_cfg_space_read()
2263 unsigned int reg_offset, in al_pcie_local_cfg_space_write() argument
2271 uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset]; in al_pcie_local_cfg_space_write()
/f-stack/dpdk/drivers/regex/octeontx2/
H A Dotx2_regexdev_mbox.c175 msg->reg_offset = reg; in otx2_ree_af_reg_read()
213 msg->reg_offset = reg; in otx2_ree_af_reg_write()
/f-stack/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c11445 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) || in i40e_valid_regs()
11446 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) || in i40e_valid_regs()
11447 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) || in i40e_valid_regs()
11448 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) || in i40e_valid_regs()
11449 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) || in i40e_valid_regs()
11450 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) || in i40e_valid_regs()
11451 (reg_offset >= 0x265c00 && reg_offset <= 0x266000))) in i40e_valid_regs()
11482 ptr_data[reg_offset >> 2] = in i40e_get_regs()
11499 ptr_data[reg_offset >> 2] = 0; in i40e_get_regs()
11501 ptr_data[reg_offset >> 2] = in i40e_get_regs()
[all …]
/f-stack/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c3958 int reg_offset; in bnx2x_attn_int_deasserted2() local
4034 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted2()
4036 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted2()
4048 int reg_offset; in bnx2x_attn_int_deasserted1() local
4064 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted1()
4066 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted1()
4078 int reg_offset; in bnx2x_attn_int_deasserted0() local
4085 val = REG_RD(sc, reg_offset); in bnx2x_attn_int_deasserted0()
4087 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted0()
4105 REG_WR(sc, reg_offset, val); in bnx2x_attn_int_deasserted0()
[all …]
H A Decore_sp.c719 uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM : in ecore_set_mac_in_nig() local
733 reg_offset += 8 * index; in ecore_set_mac_in_nig()
739 ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2); in ecore_set_mac_in_nig()
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_82575.c2093 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2097 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2101 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2107 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2119 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/f-stack/dpdk/drivers/net/qede/
H A Dqede_debug.c1984 u32 offset = 0, reg_offset = 0; in qed_grc_dump_reg_entry_skip() local
1991 while (reg_offset < total_len) { in qed_grc_dump_reg_entry_skip()
1993 total_len - reg_offset); in qed_grc_dump_reg_entry_skip()
2000 reg_offset += curr_len; in qed_grc_dump_reg_entry_skip()
2003 if (reg_offset < total_len) { in qed_grc_dump_reg_entry_skip()
2008 reg_offset += curr_len; in qed_grc_dump_reg_entry_skip()
3582 rule->reg_offset; in qed_idle_chk_dump_failure()
3723 rule->reg_offset; in qed_idle_chk_dump_rule_entries()
/f-stack/dpdk/drivers/common/octeontx2/
H A Dotx2_mbox.h1241 uint64_t __otx2_io reg_offset; member
1747 uint64_t __otx2_io reg_offset; member