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Searched refs:reg_base (Results 1 – 21 of 21) sorted by relevance

/f-stack/freebsd/arm64/broadcom/brcmmdio/
H A Dmdio_mux_iproc.c98 struct resource * reg_base; member
166 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); in brcm_iproc_switch()
178 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in iproc_mdio_wait_for_idle()
207 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); in brcm_iproc_mdio_op()
208 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in brcm_iproc_mdio_op()
213 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); in brcm_iproc_mdio_op()
221 bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); in brcm_iproc_mdio_op()
223 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); in brcm_iproc_mdio_op()
320 if (sc->reg_base == NULL) { in brcm_iproc_mdio_attach()
393 if (sc->reg_base != NULL) { in brcm_iproc_mdio_detach()
[all …]
/f-stack/dpdk/drivers/common/octeontx2/
H A Dotx2_mbox.c38 mbox->reg_base = 0; in otx2_mbox_fini()
64 otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base, in otx2_mbox_init() argument
71 mbox->reg_base = reg_base; in otx2_mbox_init()
221 rte_write64(1, (volatile void *)(mbox->reg_base + in otx2_mbox_msg_send()
263 reg_addr = mbox->reg_base + mbox->intr_offset; in mbox_poll()
H A Dotx2_mbox.h67 uintptr_t reg_base;/* CSR base for this dev */ member
1775 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
/f-stack/dpdk/drivers/crypto/ccp/
H A Dccp_dev.c536 cmd_q->reg_base = (uint8_t *)vaddr + in ccp_add_device()
553 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_add_device()
557 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INT_ENABLE_BASE, 0x00); in ccp_add_device()
558 CCP_READ_REG(cmd_q->reg_base, CMD_Q_INT_STATUS_BASE); in ccp_add_device()
559 CCP_READ_REG(cmd_q->reg_base, CMD_Q_STATUS_BASE); in ccp_add_device()
562 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INTERRUPT_STATUS_BASE, in ccp_add_device()
570 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE, in ccp_add_device()
572 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_HEAD_LO_BASE, in ccp_add_device()
577 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_add_device()
H A Dccp_crypto.c1625 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_hmac()
1708 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_hmac()
1798 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha()
1877 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3_hmac()
1953 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3_hmac()
2019 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_sha3()
2361 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_3des()
2447 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
2489 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
2534 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE, in ccp_perform_aes_gcm()
[all …]
H A Dccp_dev.h204 void *reg_base; member
/f-stack/dpdk/drivers/net/thunderx/base/
H A Dnicvf_hw.h114 nicvf_addr_write(nic->reg_base + offset, val); in nicvf_reg_write()
120 return nicvf_addr_read(nic->reg_base + offset); in nicvf_reg_read()
126 return nic->reg_base + (qidx << NIC_Q_NUM_SHIFT); in nicvf_qset_base()
/f-stack/dpdk/drivers/crypto/octeontx/
H A Dotx_cryptodev_hw_access.h31 #define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)
78 uint8_t *reg_base; member
155 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
H A Dotx_cryptodev_hw_access.c369 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name) in otx_cpt_hw_init() argument
374 cptvf->reg_base = reg_base; in otx_cpt_hw_init()
H A Dotx_cryptodev_ops.c952 void *reg_base; in otx_cpt_dev_create() local
977 reg_base = pdev->mem_resource[0].addr; in otx_cpt_dev_create()
978 if (!reg_base) { in otx_cpt_dev_create()
984 ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name); in otx_cpt_dev_create()
/f-stack/dpdk/drivers/compress/octeontx/
H A Dotx_zip.c98 void *reg_base = qp->vf->vbar0; in zipvf_push_command() local
134 zip_reg_write64(reg_base, ZIP_VQ_DOORBELL, dbell.u); in zipvf_push_command()
/f-stack/dpdk/drivers/event/skeleton/
H A Dskeleton_eventdev.h24 uintptr_t reg_base; member
H A Dskeleton_eventdev.c362 skel->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; in skeleton_eventdev_init()
363 if (!skel->reg_base) { in skeleton_eventdev_init()
/f-stack/freebsd/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
/f-stack/dpdk/drivers/net/thunderx/
H A Dnicvf_struct.h84 uintptr_t reg_base; member
H A Dnicvf_ethdev.c2171 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; in nicvf_eth_dev_init()
2172 if (!nic->reg_base) { in nicvf_eth_dev_init()
/f-stack/freebsd/arm64/iommu/
H A Dsmmu.c902 uint64_t reg_base; in smmu_init_strtab_2lvl() local
948 reg_base = base & STRTAB_BASE_ADDR_M; in smmu_init_strtab_2lvl()
949 KASSERT(reg_base == base, ("bad allocation 3")); in smmu_init_strtab_2lvl()
950 reg_base |= STRTAB_BASE_RA; in smmu_init_strtab_2lvl()
951 strtab->base = reg_base; in smmu_init_strtab_2lvl()
/f-stack/dpdk/drivers/net/bnxt/
H A Dbnxt_ethdev.c3085 uint32_t reg_base = *reg_arr & 0xfffff000; in bnxt_map_regs() local
3090 if ((reg_arr[i] & 0xfffff000) != reg_base) in bnxt_map_regs()
3094 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); in bnxt_map_regs()
3595 uint32_t reg_base = 0xffffffff; in bnxt_map_fw_health_status_regs() local
3605 if (reg_base == 0xffffffff) in bnxt_map_fw_health_status_regs()
3606 reg_base = reg & 0xfffff000; in bnxt_map_fw_health_status_regs()
3607 if ((reg & 0xfffff000) != reg_base) in bnxt_map_fw_health_status_regs()
3617 if (reg_base == 0xffffffff) in bnxt_map_fw_health_status_regs()
3620 rte_write32(reg_base, (uint8_t *)bp->bar0 + in bnxt_map_fw_health_status_regs()
/f-stack/freebsd/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
H A Dtegra210.dtsi1568 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1569 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dtegra124.dtsi898 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
899 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */