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Searched refs:reg_addr (Results 1 – 25 of 53) sorted by relevance

123

/f-stack/dpdk/drivers/crypto/nitrox/
H A Dnitrox_hal.c22 uint64_t reg_addr; in nps_pkt_input_ring_disable() local
25 reg_addr = NPS_PKT_IN_INSTR_CTLX(ring); in nps_pkt_input_ring_disable()
43 uint64_t reg_addr; in nps_pkt_solicited_port_disable() local
47 reg_addr = NPS_PKT_SLC_CTLX(port); in nps_pkt_solicited_port_disable()
68 uint64_t base_addr, reg_addr; in setup_nps_pkt_input_ring() local
128 uint64_t reg_addr; in setup_nps_pkt_solicit_output_port() local
134 reg_addr = NPS_PKT_SLC_CNTSX(port); in setup_nps_pkt_solicit_output_port()
152 reg_addr = NPS_PKT_SLC_CTLX(port); in setup_nps_pkt_solicit_output_port()
171 uint64_t reg_addr; in vf_get_vf_config_mode() local
176 reg_addr = AQMQ_QSZX(0); in vf_get_vf_config_mode()
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/f-stack/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c314 void *reg_addr; in intel_ntb_gen3_set_link() local
340 void *reg_addr; in intel_ntb_gen4_set_link() local
355 ppd0 = rte_read32(reg_addr); in intel_ntb_gen4_set_link()
357 rte_write32(ppd0, reg_addr); in intel_ntb_gen4_set_link()
360 ppd0 = rte_read32(reg_addr); in intel_ntb_gen4_set_link()
404 void *reg_addr; in intel_ntb_spad_read() local
423 spad_v = rte_read32(reg_addr); in intel_ntb_spad_read()
434 void *reg_addr; in intel_ntb_spad_write() local
454 rte_write32(spad_v, reg_addr); in intel_ntb_spad_write()
536 void *reg_addr; in intel_ntb_vector_bind() local
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/f-stack/freebsd/contrib/octeon-sdk/
H A Dcvmx-ixf18201.c85 uint16_t cvmx_ixf18201_read16(uint16_t reg_addr) in cvmx_ixf18201_read16() argument
87 cvmx_write64_uint16(IXF_ADDR_16, reg_addr); in cvmx_ixf18201_read16()
95 void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data) in cvmx_ixf18201_write16() argument
97 cvmx_write64_uint16(IXF_ADDR_16, reg_addr); in cvmx_ixf18201_write16()
105 uint32_t cvmx_ixf18201_read32(uint16_t reg_addr) in cvmx_ixf18201_read32() argument
109 if (reg_addr & 0x1) in cvmx_ixf18201_read32()
113 lo = cvmx_ixf18201_read16(reg_addr); in cvmx_ixf18201_read32()
114 hi = cvmx_ixf18201_read16(reg_addr + 1); in cvmx_ixf18201_read32()
121 if (reg_addr & 0x1) in cvmx_ixf18201_write32()
127 cvmx_ixf18201_write16(reg_addr, lo); in cvmx_ixf18201_write32()
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H A Dcvmx-ixf18201.h63 uint16_t cvmx_ixf18201_read16(uint16_t reg_addr);
71 void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data);
79 uint32_t cvmx_ixf18201_read32(uint16_t reg_addr);
87 void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data);
/f-stack/dpdk/drivers/baseband/fpga_5gnr_fec/
H A Dfpga_5gnr_fec.h299 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
300 *((volatile uint8_t *)(reg_addr)) = payload; in fpga_reg_write_8()
307 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
308 mmio_write_16(reg_addr, payload); in fpga_reg_write_16()
315 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
316 mmio_write_32(reg_addr, payload); in fpga_reg_write_32()
323 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
324 mmio_write_64(reg_addr, payload); in fpga_reg_write_64()
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_16() local
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/f-stack/freebsd/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.c215 uint16_t reg_addr; in al_eth_an_lt_reg_read() local
222 al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr); in al_eth_an_lt_reg_read()
238 reg_addr); in al_eth_an_lt_reg_read()
248 reg_addr); in al_eth_an_lt_reg_read()
258 reg_addr); in al_eth_an_lt_reg_read()
268 reg_addr); in al_eth_an_lt_reg_read()
294 uint16_t reg_addr; in al_eth_an_lt_reg_write() local
315 reg_addr); in al_eth_an_lt_reg_write()
326 reg_addr); in al_eth_an_lt_reg_write()
337 reg_addr); in al_eth_an_lt_reg_write()
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/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_x550.h35 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
37 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
43 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
45 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
75 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
77 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_phy.h135 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
137 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
139 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
141 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.h40 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
42 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
180 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
182 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.c527 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg() argument
533 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, in ixgbe_read_phy_reg()
546 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_write_phy_reg() argument
552 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
1260 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg() argument
1263 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, in ixgbe_read_iosf_sb_reg()
1276 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg() argument
1279 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, in ixgbe_write_iosf_sb_reg()
/f-stack/dpdk/drivers/net/cxgbe/base/
H A Dt4_regs.h7 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) argument
10 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) argument
17 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) argument
20 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) argument
26 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) argument
29 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
33 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) argument
36 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) argument
H A Dadapter.h475 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() argument
477 return CXGBE_READ_REG(adapter, reg_addr); in t4_read_reg()
488 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg() argument
490 CXGBE_WRITE_REG(adapter, reg_addr, val); in t4_write_reg()
501 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, in t4_write_reg_relaxed() argument
504 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val); in t4_write_reg_relaxed()
514 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64() argument
516 return CXGBE_READ_REG64(adapter, reg_addr); in t4_read_reg64()
527 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64() argument
530 CXGBE_WRITE_REG64(adapter, reg_addr, val); in t4_write_reg64()
/f-stack/freebsd/arm/arm/
H A Ddebug_monitor.c523 uint32_t reg_addr, reg_ctrl; in dbg_find_slot() local
529 reg_addr = DBG_REG_BASE_BVR; in dbg_find_slot()
534 reg_addr = DBG_REG_BASE_WVR; in dbg_find_slot()
597 uint32_t reg_ctrl, reg_addr, ctrl, addr; in dbg_setup_xpoint() local
655 reg_addr = DBG_REG_BASE_BVR; in dbg_setup_xpoint()
675 reg_addr = DBG_REG_BASE_WVR; in dbg_setup_xpoint()
681 dbg_wb_write_reg(reg_addr, i, addr); in dbg_setup_xpoint()
712 uint32_t reg_ctrl, reg_addr, addr; in dbg_remove_xpoint() local
726 reg_addr = DBG_REG_BASE_BVR; in dbg_remove_xpoint()
734 reg_addr = DBG_REG_BASE_WVR; in dbg_remove_xpoint()
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/f-stack/freebsd/contrib/alpine-hal/
H A Dal_hal_udma_main.c109 uint32_t *reg_addr; in al_udma_q_config() local
113 reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask; in al_udma_q_config()
115 val = al_reg_read32(reg_addr); in al_udma_q_config()
118 al_reg_write32(reg_addr, val); in al_udma_q_config()
132 uint32_t *reg_addr; in al_udma_q_config_compl() local
136 reg_addr = &udma_q->q_regs->m2s_q.comp_cfg; in al_udma_q_config_compl()
138 reg_addr = &udma_q->q_regs->s2m_q.comp_cfg; in al_udma_q_config_compl()
140 val = al_reg_read32(reg_addr); in al_udma_q_config_compl()
152 al_reg_write32(reg_addr, val); in al_udma_q_config_compl()
/f-stack/dpdk/drivers/net/bnx2x/
H A Decore_init.h215 uint32_t reg_addr, reg_bit_map, vnic; in ecore_map_q_cos() local
236 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in ecore_map_q_cos()
237 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
238 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
241 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in ecore_map_q_cos()
242 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
243 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
248 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); in ecore_map_q_cos()
249 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
254 REG_WR(sc, reg_addr, reg_bit_map); in ecore_map_q_cos()
/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.h331 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
333 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
335 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
337 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
/f-stack/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_api_cmd.c442 u32 reg_addr, val; in api_cmd_hw_restart() local
446 reg_addr = HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(chain->chain_type); in api_cmd_hw_restart()
447 val = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_hw_restart()
452 hinic_hwif_write_reg(hwif, reg_addr, val); in api_cmd_hw_restart()
457 val = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_hw_restart()
477 u32 reg_addr, ctrl; in api_cmd_ctrl_init() local
481 reg_addr = HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(chain->chain_type); in api_cmd_ctrl_init()
486 ctrl = hinic_hwif_read_reg(hwif, reg_addr); in api_cmd_ctrl_init()
494 hinic_hwif_write_reg(hwif, reg_addr, ctrl); in api_cmd_ctrl_init()
/f-stack/dpdk/drivers/crypto/ccp/
H A Dccp_dev.h154 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_write() local
156 rte_write32((rte_cpu_to_le_32(value)), reg_addr); in ccp_pci_reg_write()
161 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_read() local
163 return rte_le_to_cpu_32(rte_read32(reg_addr)); in ccp_pci_reg_read()
/f-stack/dpdk/drivers/common/octeontx2/
H A Dotx2_mbox.c261 uintptr_t reg_addr; in mbox_poll() local
263 reg_addr = mbox->reg_base + mbox->intr_offset; in mbox_poll()
265 rsp_reg = otx2_read64(reg_addr); in mbox_poll()
277 otx2_write64(rsp_reg, reg_addr); in mbox_poll()
/f-stack/dpdk/drivers/baseband/acc100/
H A Drte_acc100_pmd.c44 mmio_write(reg_addr, value); in acc100_reg_write()
54 uint32_t ret = *((volatile uint32_t *)(reg_addr)); in acc100_reg_read()
212 const struct acc100_registry_addr *reg_addr; in fetch_acc100_config() local
223 reg_addr = &pf_reg_addr; in fetch_acc100_config()
225 reg_addr = &vf_reg_addr; in fetch_acc100_config()
558 const struct acc100_registry_addr *reg_addr; in allocate_info_ring() local
567 reg_addr = &pf_reg_addr; in allocate_info_ring()
569 reg_addr = &vf_reg_addr; in allocate_info_ring()
602 const struct acc100_registry_addr *reg_addr; in acc100_setup_queues() local
635 reg_addr = &pf_reg_addr; in acc100_setup_queues()
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/f-stack/freebsd/arm64/arm64/
H A Ddebug_monitor.c317 uint64_t *reg_addr, *reg_ctrl; in dbg_find_slot() local
323 reg_addr = monitor->dbg_bvr; in dbg_find_slot()
328 reg_addr = monitor->dbg_wvr; in dbg_find_slot()
337 if (reg_addr[i] == addr && in dbg_find_slot()
/f-stack/dpdk/drivers/net/ixgbe/
H A Drte_pmd_ixgbe.h627 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
651 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
/f-stack/dpdk/drivers/baseband/fpga_lte_fec/
H A Dfpga_lte_fec.c292 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
293 *((volatile uint8_t *)(reg_addr)) = payload; in fpga_reg_write_8()
300 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
301 mmio_write_16(reg_addr, payload); in fpga_reg_write_16()
308 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
309 mmio_write_32(reg_addr, payload); in fpga_reg_write_32()
316 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
317 mmio_write_64(reg_addr, payload); in fpga_reg_write_64()
346 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
356 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_8() local
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/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_prototype.h99 u32 reg_addr, u64 reg_val,
102 u32 reg_addr, u64 *reg_val,
562 u32 reg_addr, u32 *reg_val,
564 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
566 u32 reg_addr, u32 reg_val,
568 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
573 u32 reg_addr, u32 reg_val,
579 u32 reg_addr, u32 *reg_val,
/f-stack/dpdk/drivers/common/mlx5/linux/
H A Dmlx5_common_os.h174 return ((struct mlx5dv_devx_uar *)uar)->reg_addr; in mlx5_os_get_devx_uar_reg_addr()

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