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Searched refs:rd32 (Results 1 – 25 of 31) sorted by relevance

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/f-stack/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_hw.c377 rd32(hw, TXGBE_DMARXPKT); in txgbe_clear_hw_cntrs()
378 rd32(hw, TXGBE_DMATXPKT); in txgbe_clear_hw_cntrs()
413 rd32(hw, TXGBE_FCOECRC); in txgbe_clear_hw_cntrs()
414 rd32(hw, TXGBE_FCOELAST); in txgbe_clear_hw_cntrs()
415 rd32(hw, TXGBE_FCOERPDC); in txgbe_clear_hw_cntrs()
416 rd32(hw, TXGBE_FCOEPRC); in txgbe_clear_hw_cntrs()
417 rd32(hw, TXGBE_FCOEPTC); in txgbe_clear_hw_cntrs()
418 rd32(hw, TXGBE_FCOEDWRC); in txgbe_clear_hw_cntrs()
419 rd32(hw, TXGBE_FCOEDWTC); in txgbe_clear_hw_cntrs()
423 rd32(hw, TXGBE_FDIRMISS); in txgbe_clear_hw_cntrs()
[all …]
H A Dtxgbe_dcb.c52 mflcn_reg = rd32(hw, TXGBE_RXFCCFG); in txgbe_dcb_pfc_enable()
55 fccfg_reg = rd32(hw, TXGBE_TXFCCFG); in txgbe_dcb_pfc_enable()
66 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i)); in txgbe_dcb_pfc_enable()
89 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i)); in txgbe_dcb_pfc_enable()
133 fcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32; in txgbe_dcb_pfc_enable()
H A Dtxgbe_mbx.c123 u32 mbvficr = rd32(hw, TXGBE_MBVFICR(index)); in txgbe_check_for_bit_pf()
198 vflre = rd32(hw, TXGBE_FLRVFE(reg_offset)); in txgbe_check_for_rst_pf()
226 p2v_mailbox = rd32(hw, TXGBE_MBCTL(vf_number)); in txgbe_obtain_mbx_lock_pf()
H A Dtxgbe_eeprom.c40 eec = rd32(hw, TXGBE_SPISTAT); in txgbe_init_eeprom_params()
89 swsm = rd32(hw, TXGBE_SWSEM); in txgbe_get_eeprom_semaphore()
114 swsm = rd32(hw, TXGBE_SWSEM); in txgbe_get_eeprom_semaphore()
130 swsm = rd32(hw, TXGBE_MNGSWSYNC); in txgbe_get_eeprom_semaphore()
H A Dtxgbe_regs.h1759 rd32(struct txgbe_hw *hw, u32 reg) in rd32() function
1777 u32 val = rd32(hw, reg); in rd32m()
1785 u32 val = rd32(hw, reg); in wr32m()
1793 u64 lsb = rd32(hw, reg); in rd64()
1794 u64 msb = rd32(hw, reg + 4); in rd64()
1819 all |= rd32(hw, reg); in po32m()
1834 #define txgbe_flush(hw) rd32(hw, 0x00100C)
1837 rd32((hw), (reg) + ((idx) << 2)))
1842 rd32((hw), reg); \
1860 data = rd32(hw, TXGBE_XPCS_IDADATA); in rd32_epcs()
[all …]
H A Dtxgbe_dcb_hw.c233 reg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576; in txgbe_dcb_config_pfc_raptor()
/f-stack/dpdk/drivers/net/txgbe/
H A Dtxgbe_ethdev.c978 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_vlan_hw_extend_disable()
994 ctrl = rd32(hw, TXGBE_PORTCTL); in txgbe_vlan_hw_extend_enable()
1871 rd32(hw, TXGBE_PBRXMISS(i)); in txgbe_read_stats_registers()
2507 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_promiscuous_enable()
2520 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_promiscuous_disable()
2537 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_allmulticast_enable()
2553 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_dev_allmulticast_disable()
3329 mask = rd32(hw, TXGBE_IMS(0)); in txgbe_dev_rx_queue_intr_enable()
3333 mask = rd32(hw, TXGBE_IMS(1)); in txgbe_dev_rx_queue_intr_enable()
3417 gpie = rd32(hw, TXGBE_GPIE); in txgbe_configure_msix()
[all …]
H A Dtxgbe_pf.c223 vtctl = rd32(hw, TXGBE_POOLCTL); in txgbe_pf_host_configure()
254 gpie = rd32(hw, TXGBE_GPIE); in txgbe_pf_host_configure()
256 gcr_ext = rd32(hw, TXGBE_PORTCTL); in txgbe_pf_host_configure()
277 vlanctrl = rd32(hw, TXGBE_VLANCTL); in txgbe_pf_host_configure()
291 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 32; in txgbe_pf_host_configure()
384 reg = rd32(hw, TXGBE_POOLTXENA(reg_offset)); in txgbe_vf_reset_msg()
410 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); in txgbe_disable_vf_mc_promisc()
483 u32 vmolr = rd32(hw, TXGBE_POOLETHCTL(vf)); in txgbe_vf_set_multicast()
639 vmvir = rd32(hw, TXGBE_POOLTAG(vf)); in txgbe_get_vf_queues()
704 fctrl = rd32(hw, TXGBE_PSRCTL); in txgbe_set_vf_mc_promisc()
[all …]
H A Dtxgbe_rxtx.c2809 mrqc = rd32(hw, TXGBE_RACTL); in txgbe_dev_rss_hash_update()
2861 mrqc = rd32(hw, TXGBE_RACTL); in txgbe_dev_rss_hash_conf_get()
3042 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_dcb_tx_hw_config()
3047 reg = rd32(hw, TXGBE_PORTCTL); in txgbe_dcb_tx_hw_config()
3058 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_dcb_tx_hw_config()
3229 reg = rd32(hw, TXGBE_PORTCTL); in txgbe_dcb_rx_hw_config()
3696 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_vmdq_tx_hw_configure()
3710 reg = rd32(hw, TXGBE_ARBTXCTL); in txgbe_vmdq_tx_hw_configure()
3760 mrqc = rd32(hw, TXGBE_PORTCTL); in txgbe_config_vf_rss()
3787 mrqc = rd32(hw, TXGBE_PORTCTL); in txgbe_config_vf_default()
[all …]
H A Dtxgbe_regs_group.h25 reg_buf[i] = rd32(hw, in txgbe_read_regs()
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_diag.c39 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
43 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
50 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
H A Di40e_adminq.c305 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
355 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
791 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
793 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
832 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
872 val = rd32(hw, hw->aq.asq.head);
1030 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
1105 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1107 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
1110 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
[all …]
H A Di40e_lan_hmc.c106 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
109 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
126 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
132 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
149 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
155 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
172 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
178 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
H A Di40e_common.c385 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
395 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
1332 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_poll_globr()
1370 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
1382 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
1405 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
1409 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
1451 val = rd32(hw, I40E_GLPCI_CNF2); in i40e_clear_hw()
1457 val = rd32(hw, I40E_PFLAN_QALLOC); in i40e_clear_hw()
6886 i = rd32(hw, I40E_PFGEN_PORTNUM); in i40e_blink_phy_link_led()
[all …]
H A Di40e_nvm.c31 gens = rd32(hw, I40E_GLNVM_GENS); in i40e_init_nvm()
38 fla = rd32(hw, I40E_GLNVM_FLA); in i40e_init_nvm()
75 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
90 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
158 srctl = rd32(hw, I40E_GLNVM_SRCTL); in i40e_poll_sr_srctl_done_bit()
206 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); in i40e_read_nvm_word_srctl()
1302 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_nvmupd_state_writing()
H A Di40e_osdep.h153 #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) macro
/f-stack/freebsd/mips/cavium/
H A Doctopci_bus_space.c201 #define rd32(a) le32toh(cvmx_read64_uint32(a)) macro
258 return (rd32(handle + offset)); in octopci_bs_r_4()
287 *addr++ = rd32(baddr); in octopci_bs_rm_4()
326 *addr++ = rd32(baddr); in octopci_bs_rr_4()
556 wr32(addr2, rd32(addr1)); in octopci_bs_c_4()
561 wr32(addr2, rd32(addr1)); in octopci_bs_c_4()
/f-stack/freebsd/mips/malta/
H A Dgt_pci_bus_space.c221 #define rd32(a) le32toh(readl(a)) macro
241 return (rd32(handle + offset)); in gt_pci_bs_r_4()
261 *addr++ = rd32(baddr); in gt_pci_bs_rm_4()
288 *addr++ = rd32(baddr); in gt_pci_bs_rr_4()
/f-stack/freebsd/mips/mips/
H A Dbus_space_generic.c199 #define rd32(a) cvmx_read64_uint32(a) macro
208 #define rd32(a) readl(a) macro
289 return (rd32(handle + offset)); in generic_bs_r_4()
329 *addr++ = rd32(baddr); in generic_bs_rm_4()
382 *addr++ = rd32(baddr); in generic_bs_rr_4()
698 wr32(addr2, rd32(addr1)); in generic_bs_c_4()
703 wr32(addr2, rd32(addr1)); in generic_bs_c_4()
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_controlq.c68 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask | in ice_check_sq_alive()
245 if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa)) in ice_cfg_cq_regs()
794 while (rd32(hw, cq->sq.head) != ntc) { in ice_clean_sq()
795 ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head)); in ice_clean_sq()
870 return rd32(hw, cq->sq.head) == cq->sq.next_to_use; in ice_sq_done()
929 val = rd32(hw, cq->sq.head); in ice_sq_send_cmd_nolock()
1038 if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask || in ice_sq_send_cmd_nolock()
1039 rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) { in ice_sq_send_cmd_nolock()
1134 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
1191 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask); in ice_clean_rq_elem()
H A Dice_common.c653 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & in ice_get_itr_intrl_gran()
710 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & in ice_init_hw()
894 reg = rd32(hw, GLGEN_RSTAT); in ice_check_reset()
916 reg = rd32(hw, GLNVM_ULD) & uld_mask; in ice_check_reset()
949 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || in ice_pf_reset()
959 reg = rd32(hw, PFGEN_CTRL); in ice_pf_reset()
969 reg = rd32(hw, PFGEN_CTRL); in ice_pf_reset()
1015 val |= rd32(hw, GLGEN_RTRIG); in ice_reset()
1954 reg_val = rd32(hw, GLQF_FD_SIZE); in ice_parse_fdir_func_caps()
4495 new_data = rd32(hw, reg); in ice_stat_update32()
[all …]
H A Dice_osdep.h119 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
170 #define ICE_READ_REG(hw, reg) rd32(hw, reg)
H A Dice_nvm.c843 gens_stat = rd32(hw, GLNVM_GENS); in ice_init_nvm()
850 fla = rd32(hw, GLNVM_FLA); in ice_init_nvm()
1089 data->regval = rd32(hw, cmd->offset); in ice_nvm_access_read()
/f-stack/dpdk/drivers/common/iavf/
H A Diavf_adminq.c272 reg = rd32(hw, hw->aq.asq.bal); in iavf_config_asq_regs()
304 reg = rd32(hw, hw->aq.arq.bal); in iavf_config_arq_regs()
591 while (rd32(hw, hw->aq.asq.head) != ntc) { in iavf_clean_asq()
593 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in iavf_clean_asq()
628 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in iavf_asq_done()
668 val = rd32(hw, hw->aq.asq.head); in iavf_asq_send_command()
825 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { in iavf_asq_send_command()
895 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK; in iavf_clean_arq_element()
H A Diavf_osdep.h111 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
126 #define IAVF_READ_REG(hw, reg) rd32(hw, reg)

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