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Searched refs:rates (Results 1 – 25 of 311) sorted by relevance

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/f-stack/freebsd/arm64/rockchip/clk/
H A Drk_clk_pll.c218 if (sc->rates == NULL) in rk3066_clk_pll_set_freq()
221 for (rates = sc->rates; rates->freq; rates++) { in rk3066_clk_pll_set_freq()
335 sc->rates = clkdef->rates; in rk3066_clk_pll_register()
441 if (sc->rates) in rk3328_clk_pll_set_freq()
442 rates = sc->rates; in rk3328_clk_pll_set_freq()
448 for (; rates->freq; rates++) { in rk3328_clk_pll_set_freq()
541 sc->rates = clkdef->rates; in rk3328_clk_pll_register()
685 if (sc->rates) in rk3399_clk_pll_set_freq()
686 rates = sc->rates; in rk3399_clk_pll_set_freq()
692 for (; rates->freq; rates++) { in rk3399_clk_pll_set_freq()
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H A Drk_clk_armclk.c61 struct rk_clk_armclk_rates *rates; member
163 if (sc->rates[i].freq == *fout) { in rk_clk_armclk_set_freq()
164 best = sc->rates[i].freq; in rk_clk_armclk_set_freq()
165 div = sc->rates[i].div; in rk_clk_armclk_set_freq()
251 sc->rates = clkdef->rates; in rk_clk_armclk_register()
H A Drk_clk_armclk.h56 struct rk_clk_armclk_rates *rates; member
/f-stack/freebsd/netinet/
H A Dtcp_stats.c75 struct stats_tpl_sample_rate **rates, int *nrates, void *ctx);
220 struct stats_tpl_sample_rate **rates, int *nrates, void *ctx) in tcp_stats_tpl_sr_cb() argument
239 if (rates != NULL) in tcp_stats_tpl_sr_cb()
240 *rates = V_tcp_perconn_stats_sample_rates; in tcp_stats_tpl_sr_cb()
250 KASSERT(rates != NULL && nrates != NULL, in tcp_stats_tpl_sr_cb()
253 if (rates == NULL || nrates == NULL) in tcp_stats_tpl_sr_cb()
258 V_tcp_perconn_stats_sample_rates = *rates; in tcp_stats_tpl_sr_cb()
261 *rates = old_rates; in tcp_stats_tpl_sr_cb()
/f-stack/freebsd/contrib/device-tree/Bindings/serial/
H A Dnvidia,tegra20-hsuart.txt27 - nvidia,adjust-baud-rates: List of entries providing percentage of baud rate
46 Tx baud rate observed. To do this we use nvidia,adjust-baud-rates
48 As an example, consider there is deviation observed in Tx for baud rates as
56 nvidia,adjust-baud-rates = <0 9600 100>,
72 nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */
/f-stack/freebsd/net80211/
H A Dieee80211_adhoc.c685 is11bclient(const uint8_t *rates, const uint8_t *xrates) in is11bclient() argument
691 if (xrates != NULL || rates == NULL) in is11bclient()
693 for (i = 0; i < rates[1]; i++) { in is11bclient()
694 int r = rates[2+i] & IEEE80211_RATE_VAL; in is11bclient()
710 uint8_t *ssid, *rates, *xrates; in adhoc_recv_mgmt() local
904 ssid = rates = xrates = NULL; in adhoc_recv_mgmt()
912 rates = frm; in adhoc_recv_mgmt()
920 IEEE80211_VERIFY_ELEMENT(rates, IEEE80211_RATE_MAXSIZE, return); in adhoc_recv_mgmt()
923 IEEE80211_RATE_MAXSIZE - rates[1], return); in adhoc_recv_mgmt()
944 is11bclient(rates, xrates) ? IEEE80211_SEND_LEGACY_11B : 0); in adhoc_recv_mgmt()
/f-stack/freebsd/contrib/device-tree/src/mips/img/
H A Dpistachio.dtsi53 assigned-clock-rates = <100000000>, <33333334>;
71 assigned-clock-rates = <100000000>, <33333334>;
89 assigned-clock-rates = <100000000>, <33333334>;
107 assigned-clock-rates = <100000000>, <33333334>;
142 assigned-clock-rates = <12288000>;
162 assigned-clock-rates = <12288000>;
179 assigned-clock-rates = <12288000>;
752 assigned-clock-rates = <4000000>, <32768>;
763 assigned-clock-rates = <4000000>, <32768>;
789 assigned-clock-rates = <0>, <50000000>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/display/hisilicon/
H A Dhisi-ade.txt22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
56 assigned-clock-rates = <360000000>, <288000000>;
/f-stack/freebsd/contrib/device-tree/Bindings/mtd/
H A Dvf610-nfc.txt13 - assigned-clock-rates: The NAND bus timing is derived from this clock
17 there might be restrictions on maximum rates when using hardware ECC.
48 assigned-clock-rates = <33000000>;
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-typec.txt13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
47 assigned-clock-rates = <50000000>;
71 assigned-clock-rates = <50000000>;
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra210-ahub.yaml48 assigned-clock-rates:
118 assigned-clock-rates = <1536000>;
129 assigned-clock-rates = <3072000>;
H A Dbrcm,cygnus-audio.txt16 - assigned-clock-rates: List of clock frequencies of the
41 assigned-clock-rates = <1769470191>,
H A Dnvidia,tegra210-dmic.yaml47 assigned-clock-rates:
78 assigned-clock-rates = <3072000>;
H A Dst,stm32-i2s.yaml31 - description: I2S parent clock for sampling rates multiple of 8kHz.
32 - description: I2S parent clock for sampling rates multiple of 11.025kHz.
H A Dnvidia,tegra186-dspk.yaml46 assigned-clock-rates:
78 assigned-clock-rates = <12288000>;
/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dsdhci-atmel.txt16 - assigned-clock-rates The rate of "multclk" in order to not rely on the
32 assigned-clock-rates = <480000000>;
/f-stack/freebsd/contrib/device-tree/Bindings/ata/
H A Dqcom-sata.txt25 - assigned-clock-rates : Shall be:
44 assigned-clock-rates = <100000000>, <100000000>;
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dexynos5422-odroidxu4.dts53 assigned-clock-rates = <0>,
75 assigned-clock-rates = <(196608000 / 256)>,
H A Dexynos5422-odroidxu3-audio.dtsi47 assigned-clock-rates = <0>,
68 assigned-clock-rates = <(196608000 / 256)>,
H A Dimx7ulp.dtsi156 assigned-clock-rates = <24000000>;
168 assigned-clock-rates = <48000000>;
335 assigned-clock-rates = <48000000>;
347 assigned-clock-rates = <48000000>;
359 assigned-clock-rates = <48000000>;
371 assigned-clock-rates = <48000000>;
H A Dexynos4412-odroid-common.dtsi145 assigned-clock-rates = <45158401>;
158 assigned-clock-rates = <0>, <0>,
214 assigned-clock-rates = <0>, <176000000>;
222 assigned-clock-rates = <0>, <176000000>;
230 assigned-clock-rates = <0>, <176000000>;
238 assigned-clock-rates = <0>, <176000000>;
H A Dvf610-colibri.dtsi21 assigned-clock-rates = <50000000>;
/f-stack/freebsd/contrib/device-tree/Bindings/display/msm/
H A Ddpu.txt39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
88 assigned-clock-rates = <300000000>;
118 assigned-clock-rates = <0 0 300000000 19200000>;
/f-stack/freebsd/contrib/device-tree/Bindings/display/rockchip/
H A Dcdn-dp-rockchip.txt20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
45 assigned-clock-rates = <100000000>;
/f-stack/freebsd/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-sr-som.dtsi165 assigned-clock-rates = <25000000>;
174 assigned-clock-rates = <80000000>;
180 assigned-clock-rates = <400000000>;

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