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Searched refs:q_id (Results 1 – 25 of 47) sorted by relevance

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/f-stack/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_eqs.c127 if (eq->q_id == 0) in set_eq_cons_idx()
314 eq->q_id = q_id; in init_aeq()
357 if (eq->q_id == 0) in init_aeq()
402 u16 i, q_id; in hinic_aeqs_init() local
412 for (q_id = HINIC_AEQN_START; q_id < num_aeqs; q_id++) { in hinic_aeqs_init()
413 err = init_aeq(&aeqs->aeq[q_id], hwdev, q_id, in hinic_aeqs_init()
440 u16 q_id; in hinic_aeqs_free() local
443 for (q_id = HINIC_AEQN_START; q_id < aeqs->num_aeqs ; q_id++) in hinic_aeqs_free()
453 int q_id; in hinic_dump_aeq_info() local
455 for (q_id = 0; q_id < hwdev->aeqs->num_aeqs; q_id++) { in hinic_dump_aeq_info()
[all …]
H A Dhinic_pmd_nicio.h24 #define HINIC_CI_VADDR(base_addr, q_id) \ argument
25 ((u8 *)(base_addr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
27 #define HINIC_CI_PADDR(base_paddr, q_id) \ argument
28 ((base_paddr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
33 #define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \ argument
35 (q_id) * Q_CTXT_SIZE)
37 #define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \ argument
39 (max_sqs) * Q_CTXT_SIZE + (q_id) * Q_CTXT_SIZE)
177 u16 q_id; member
189 u16 q_id; member
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H A Dhinic_pmd_nicio.c287 q_id = 0; in init_sq_ctxts()
289 while (q_id < nic_io->num_sqs) { in init_sq_ctxts()
298 nic_io->max_qps, q_id); in init_sq_ctxts()
301 curr_id = q_id + i; in init_sq_ctxts()
321 q_id += max_ctxts; in init_sq_ctxts()
346 q_id = 0; in init_rq_ctxts()
360 curr_id = q_id + i; in init_rq_ctxts()
378 q_id += max_ctxts; in init_rq_ctxts()
545 u16 q_id; in hinic_init_qp_ctxts() local
594 for (q_id = 0; q_id < nic_io->num_sqs; q_id++) { in hinic_init_qp_ctxts()
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H A Dhinic_csr.h59 #define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) \ argument
60 (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
63 #define HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) \ argument
64 (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
67 #define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num) \ argument
68 ((u32)(HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
70 #define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num) \ argument
71 ((u32)(HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
/f-stack/dpdk/lib/librte_ethdev/
H A Dethdev_profile.c41 uint16_t q_id; in vtune_profile_rx_init() local
43 for (q_id = 0; q_id < rx_queue_num; ++q_id) { in vtune_profile_rx_init()
45 port_id, q_id, profile_hook_rx_burst_cb, NULL)) { in vtune_profile_rx_init()
/f-stack/dpdk/drivers/net/hinic/
H A Dhinic_pmd_rx.c194 u16 q_id; in hinic_get_func_rx_buf_size() local
197 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { in hinic_get_func_rx_buf_size()
198 rxq = nic_dev->rxqs[q_id]; in hinic_get_func_rx_buf_size()
203 if (q_id == 0) in hinic_get_func_rx_buf_size()
222 rq->q_id = q_id; in hinic_create_rq()
411 u16 q_id; in hinic_free_all_rx_resources() local
415 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { in hinic_free_all_rx_resources()
424 kfree(nic_dev->rxqs[q_id]); in hinic_free_all_rx_resources()
425 nic_dev->rxqs[q_id] = NULL; in hinic_free_all_rx_resources()
433 u16 q_id; in hinic_free_all_rx_mbuf() local
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H A Dhinic_pmd_tx.c1115 SQ_DB_INFO_SET(sq->q_id, QID); in hinic_sq_write_db()
1222 txq->q_id) + 1; in hinic_free_all_tx_mbufs()
1245 u16 q_id; in hinic_free_all_tx_resources() local
1249 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { in hinic_free_all_tx_resources()
1261 kfree(nic_dev->txqs[q_id]); in hinic_free_all_tx_resources()
1262 nic_dev->txqs[q_id] = NULL; in hinic_free_all_tx_resources()
1268 u16 q_id; in hinic_free_all_tx_mbuf() local
1272 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) in hinic_free_all_tx_mbuf()
1332 sq->q_id = q_id; in hinic_create_sq()
1333 sq->wq = &nic_io->sq_wq[q_id]; in hinic_create_sq()
[all …]
H A Dhinic_pmd_rx.h82 u16 q_id; member
130 int hinic_create_rq(struct hinic_hwdev *hwdev, u16 q_id,
133 void hinic_destroy_rq(struct hinic_hwdev *hwdev, u16 q_id);
H A Dhinic_pmd_tx.h116 u16 q_id; member
143 int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id,
146 void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id);
H A Dhinic_pmd_ethdev.c464 rxq->q_id = queue_idx; in hinic_rx_queue_setup()
503 int q_id = 0; in hinic_reset_rx_queue() local
507 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { in hinic_reset_rx_queue()
603 txq->q_id = queue_idx; in hinic_tx_queue_setup()
646 int q_id = 0; in hinic_reset_tx_queue() local
652 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { in hinic_reset_tx_queue()
662 q_id); in hinic_reset_tx_queue()
1146 u16 q_id; in hinic_free_all_rq() local
1148 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) in hinic_free_all_rq()
1154 u16 q_id; in hinic_free_all_sq() local
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/f-stack/dpdk/drivers/baseband/null/
H A Dbbdev_null.c85 q_release(struct rte_bbdev *dev, uint16_t q_id) in q_release() argument
87 struct bbdev_queue *q = dev->data->queues[q_id].queue_private; in q_release()
92 dev->data->queues[q_id].queue_private = NULL; in q_release()
96 dev->data->dev_id, q_id); in q_release()
102 q_setup(struct rte_bbdev *dev, uint16_t q_id, in q_setup() argument
108 dev->data->dev_id, q_id); in q_setup()
125 dev->data->queues[q_id].queue_private = q; in q_setup()
/f-stack/dpdk/drivers/baseband/fpga_5gnr_fec/
H A Drte_fpga_5gnr_fec.c213 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in fpga_setup_queues()
215 FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2)); in fpga_setup_queues()
218 dev->device->name, q_id, hw_q_id); in fpga_setup_queues()
303 uint32_t q_id = 0; in fpga_dev_info_get() local
378 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in fpga_dev_info_get()
2002 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in rte_fpga_5gnr_fec_configure()
2063 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in rte_fpga_5gnr_fec_configure()
2090 for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id]; in rte_fpga_5gnr_fec_configure()
2091 ++q_id, ++total_ul_q_id) { in rte_fpga_5gnr_fec_configure()
2101 for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id]; in rte_fpga_5gnr_fec_configure()
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/f-stack/dpdk/drivers/event/opdl/
H A Dopdl_test.c779 uint8_t q_id = 0; in qid_basic() local
797 q_id = i; in qid_basic()
801 &q_id, in qid_basic()
811 q_id); in qid_basic()
895 q_id = 0; in qid_basic()
898 q_id, in qid_basic()
931 if (ev[0].queue_id != q_id) { in qid_basic()
937 q_id); in qid_basic()
943 ++q_id, in qid_basic()
955 q_id); in qid_basic()
/f-stack/dpdk/examples/bbdev_app/
H A Dmain.c946 unsigned int q_id, dec_q_id, enc_q_id; in prepare_bbdev_device() local
963 for (q_id = 0, dec_q_id = 0; q_id < dec_qs_nb; q_id++) { in prepare_bbdev_device()
964 ret = rte_bbdev_queue_configure(dev_id, q_id, &qconf); in prepare_bbdev_device()
968 ret, dev_id, q_id); in prepare_bbdev_device()
969 app_params->dec_queue_ids[dec_q_id++] = q_id; in prepare_bbdev_device()
975 for (q_id = dec_qs_nb, enc_q_id = 0; q_id < tot_qs; q_id++) { in prepare_bbdev_device()
976 ret = rte_bbdev_queue_configure(dev_id, q_id, &qconf); in prepare_bbdev_device()
980 ret, dev_id, q_id); in prepare_bbdev_device()
981 app_params->enc_queue_ids[enc_q_id++] = q_id; in prepare_bbdev_device()
/f-stack/dpdk/drivers/baseband/fpga_lte_fec/
H A Dfpga_lte_fec.c505 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in fpga_setup_queues()
507 FPGA_LTE_FEC_QUEUE_MAP + (q_id << 2)); in fpga_setup_queues()
510 dev->device->name, q_id, hw_q_id); in fpga_setup_queues()
595 uint32_t q_id = 0; in fpga_dev_info_get() local
650 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in fpga_dev_info_get()
2490 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in rte_fpga_lte_fec_configure()
2551 for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { in rte_fpga_lte_fec_configure()
2578 for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id]; in rte_fpga_lte_fec_configure()
2579 ++q_id, ++total_ul_q_id) { in rte_fpga_lte_fec_configure()
2589 for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id]; in rte_fpga_lte_fec_configure()
[all …]
/f-stack/dpdk/drivers/baseband/turbo_sw/
H A Dbbdev_turbo_software.c278 dev->data->dev_id, q_id); in q_release()
301 dev->data->dev_id, q_id); in q_setup()
305 dev->data->dev_id, q_id); in q_setup()
323 q_id); in q_setup()
327 dev->data->dev_id, q_id); in q_setup()
343 dev->data->dev_id, q_id); in q_setup()
363 dev->data->dev_id, q_id); in q_setup()
384 dev->data->dev_id, q_id); in q_setup()
405 dev->data->dev_id, q_id); in q_setup()
426 dev->data->dev_id, q_id); in q_setup()
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/f-stack/dpdk/examples/l3fwd/
H A Dl3fwd_event_internal_port.c197 uint8_t q_id = 0; in l3fwd_rx_tx_adapter_setup_internal_port() local
230 eth_q_conf.ev.queue_id = evt_rsrc->evq.event_q_id[q_id]; in l3fwd_rx_tx_adapter_setup_internal_port()
242 if (q_id < evt_rsrc->evq.nb_queues) in l3fwd_rx_tx_adapter_setup_internal_port()
243 q_id++; in l3fwd_rx_tx_adapter_setup_internal_port()
/f-stack/dpdk/examples/l2fwd-event/
H A Dl2fwd_event_internal_port.c208 uint8_t q_id = 0; in l2fwd_rx_tx_adapter_setup_internal_port() local
241 eth_q_conf.ev.queue_id = evt_rsrc->evq.event_q_id[q_id]; in l2fwd_rx_tx_adapter_setup_internal_port()
253 if (q_id < evt_rsrc->evq.nb_queues) in l2fwd_rx_tx_adapter_setup_internal_port()
254 q_id++; in l2fwd_rx_tx_adapter_setup_internal_port()
/f-stack/dpdk/drivers/crypto/octeontx2/
H A Dotx2_cryptodev_hw_access.h47 #define OTX2_CPT_LF_BAR2(vf, q_id) \ argument
49 ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
/f-stack/dpdk/examples/multi_process/symmetric_mp/
H A Dmain.c310 const uint16_t q_id = (uint16_t)proc_id; in lcore_main() local
330 printf("lcore %u using queue %u of each port\n", id, (unsigned)q_id); in lcore_main()
342 const uint16_t rx_c = rte_eth_rx_burst(src, q_id, buf, PKT_BURST); in lcore_main()
347 const uint16_t tx_c = rte_eth_tx_burst(dst, q_id, buf, rx_c); in lcore_main()
/f-stack/dpdk/drivers/raw/skeleton/
H A Dskeleton_rawdev.c416 uint16_t q_id; in skeleton_rawdev_enqueue_bufs() local
424 q_id = *((int *)context); in skeleton_rawdev_enqueue_bufs()
427 queue_buf[q_id].bufs[i] = buffers[i]->buf_addr; in skeleton_rawdev_enqueue_bufs()
438 uint16_t q_id; in skeleton_rawdev_dequeue_bufs() local
446 q_id = *((int *)context); in skeleton_rawdev_dequeue_bufs()
449 buffers[i]->buf_addr = queue_buf[q_id].bufs[i]; in skeleton_rawdev_dequeue_bufs()
/f-stack/dpdk/lib/librte_bbdev/
H A Drte_bbdev.c716 unsigned int q_id; in get_stats_from_queues() local
717 for (q_id = 0; q_id < dev->data->num_queues; q_id++) { in get_stats_from_queues()
719 &dev->data->queues[q_id].queue_stats; in get_stats_from_queues()
732 unsigned int q_id; in reset_stats_in_queues() local
733 for (q_id = 0; q_id < dev->data->num_queues; q_id++) { in reset_stats_in_queues()
735 &dev->data->queues[q_id].queue_stats; in reset_stats_in_queues()
/f-stack/dpdk/drivers/net/ark/
H A Dark_mpu.c129 ark_mpu_dump_setup(struct ark_mpu_t *mpu, uint16_t q_id) in ark_mpu_dump_setup() argument
133 q_id, in ark_mpu_dump_setup()
H A Dark_udm.c161 ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id) in ark_udm_dump_setup() argument
165 q_id, in ark_udm_dump_setup()
/f-stack/dpdk/drivers/regex/octeontx2/
H A Dotx2_regexdev_hw_access.h48 #define OTX2_REE_LF_BAR2(vf, q_id) \ argument
50 (((vf)->block_address << 20) | ((q_id) << 12)))

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