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Searched refs:pll1 (Results 1 – 25 of 25) sorted by relevance

/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dallwinner,sun4i-a10-pll1-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
H A Dqoriq-clock.txt167 pll1: pll1@820 {
172 clock-output-names = "pll1", "pll1-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
H A Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
H A Dallwinner,sun4i-a10-cpu-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
H A Dprima2-clock.txt17 pll1 2
H A Drenesas,cpg-clocks.yaml75 - const: pll1
201 - const: pll1
H A Dimx28-clock.yaml21 pll1 2
/f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
/f-stack/freebsd/contrib/device-tree/Bindings/clock/st/
H A Dst,clkgen-pll.txt13 "st,clkgen-pll1"
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Dstih410-clock.dtsi127 clk_s_c0_pll1: clk-s-c0-pll1 {
129 compatible = "st,clkgen-pll1";
133 clock-output-names = "clk-s-c0-pll1-odf-0";
H A Dstih418-clock.dtsi124 clk_s_c0_pll1: clk-s-c0-pll1 {
126 compatible = "st,clkgen-pll1";
130 clock-output-names = "clk-s-c0-pll1-odf-0";
H A Dstih407-clock.dtsi126 clk_s_c0_pll1: clk-s-c0-pll1 {
128 compatible = "st,clkgen-pll1";
132 clock-output-names = "clk-s-c0-pll1-odf-0";
H A Ddra72x.dtsi72 reg-names = "dss", "pll1_clkctrl", "pll1";
H A Ddove-cubox.dts101 /* connect xtal input as source of pll0 and pll1 */
H A Ddra74x.dtsi181 reg-names = "dss", "pll1_clkctrl", "pll1",
H A Dste-nomadik-stn8815.dtsi219 pll1: pll1@0 { label
230 clocks = <&pll1>;
H A Dda850.dtsi700 pll1: clock-controller@21a000 { label
701 compatible = "ti,da850-pll1";
H A Dsh73a0.dtsi651 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Dr8a73a4.dtsi528 clock-output-names = "main", "pll0", "pll1", "pll2",
/f-stack/freebsd/arm/nvidia/drm2/
H A Dtegra_hdmi.c133 uint32_t pll1; member
145 .pll1 = 0x00301B00,
154 .pll1 = 0x00301500,
163 .pll1 = 0x00301500,
172 .pll1 = 0x00300F00,
654 WR4(sc, HDMI_NV_PDISP_SOR_PLL1, tmds->pll1); in tmds_init()
/f-stack/freebsd/contrib/device-tree/Bindings/display/ti/
H A Dti,dra7-dss.txt24 'pll1', 'pll2_clkctrl', 'pll2'
/f-stack/freebsd/contrib/device-tree/Bindings/phy/
H A Dti,phy-j721e-wiz.yaml188 pll1-refclk {
/f-stack/freebsd/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-main.dtsi348 wiz0_pll1_refclk: pll1-refclk {
405 wiz1_pll1_refclk: pll1-refclk {
462 wiz2_pll1_refclk: pll1-refclk {
519 wiz3_pll1_refclk: pll1-refclk {