| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ti/davinci/ |
| H A D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/ |
| H A D | qoriq-clock.txt | 159 pll0: pll0@800 {
164 clock-output-names = "pll0", "pll0-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| H A D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
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| H A D | renesas,cpg-clocks.yaml | 74 - const: pll0
200 - const: pll0
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| H A D | imx28-clock.yaml | 20 pll0 1
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| /f-stack/freebsd/contrib/device-tree/src/arc/ |
| H A D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
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| H A D | abilis_tb100.dtsi | 17 pll0: oscillator { label
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| H A D | abilis_tb101.dtsi | 17 pll0: oscillator { label
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| /f-stack/freebsd/contrib/device-tree/src/arm/ |
| H A D | stih410-clock.dtsi | 77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| H A D | stih407-clock.dtsi | 77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| H A D | stih418-clock.dtsi | 78 compatible = "st,clkgen-pll0";
115 clk_s_c0_pll0: clk-s-c0-pll0 {
117 compatible = "st,clkgen-pll0";
121 clock-output-names = "clk-s-c0-pll0-odf-0";
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| H A D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
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| H A D | da850.dtsi | 135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
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| H A D | sh73a0.dtsi | 651 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | r8a73a4.dtsi | 528 clock-output-names = "main", "pll0", "pll1", "pll2",
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| /f-stack/freebsd/contrib/device-tree/Bindings/clock/st/ |
| H A D | st,clkgen-pll.txt | 12 "st,clkgen-pll0"
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| H A D | st,clkgen.txt | 51 compatible = "st,clkgen-pll0";
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| /f-stack/freebsd/arm/nvidia/drm2/ |
| H A D | tegra_hdmi.c | 132 uint32_t pll0; member
144 .pll0 = 0x01003010,
153 .pll0 = 0x01003110,
162 .pll0 = 0x01003310,
171 .pll0 = 0x01003F10,
653 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0); in tmds_init()
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| /f-stack/freebsd/contrib/device-tree/Bindings/phy/ |
| H A D | ti,phy-j721e-wiz.yaml | 181 pll0-refclk {
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| /f-stack/freebsd/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-j721e-main.dtsi | 341 wiz0_pll0_refclk: pll0-refclk {
398 wiz1_pll0_refclk: pll0-refclk {
455 wiz2_pll0_refclk: pll0-refclk {
512 wiz3_pll0_refclk: pll0-refclk {
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