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Searched refs:pll (Results 1 – 25 of 256) sorted by relevance

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/f-stack/freebsd/mips/atheros/
H A Dar934x_chip.c105 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG); in ar934x_chip_detect_sys_frequency()
106 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { in ar934x_chip_detect_sys_frequency()
112 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; in ar934x_chip_detect_sys_frequency()
133 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { in ar934x_chip_detect_sys_frequency()
139 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; in ar934x_chip_detect_sys_frequency()
292 uint32_t pll; in ar934x_chip_get_eth_pll() local
296 pll = AR934X_PLL_VAL_10; in ar934x_chip_get_eth_pll()
299 pll = AR934X_PLL_VAL_100; in ar934x_chip_get_eth_pll()
302 pll = AR934X_PLL_VAL_1000; in ar934x_chip_get_eth_pll()
306 pll = 0; in ar934x_chip_get_eth_pll()
[all …]
H A Dar91xx_chip.c70 uint32_t pll; in ar91xx_chip_detect_sys_frequency() local
76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); in ar91xx_chip_detect_sys_frequency()
119 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar91xx_chip_set_pll_ge() argument
125 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, in ar91xx_chip_set_pll_ge()
130 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, in ar91xx_chip_set_pll_ge()
166 uint32_t pll; in ar91xx_chip_get_eth_pll() local
170 pll = AR91XX_PLL_VAL_10; in ar91xx_chip_get_eth_pll()
173 pll = AR91XX_PLL_VAL_100; in ar91xx_chip_get_eth_pll()
176 pll = AR91XX_PLL_VAL_1000; in ar91xx_chip_get_eth_pll()
180 pll = 0; in ar91xx_chip_get_eth_pll()
[all …]
H A Dqca955x_chip.c87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
92 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca955x_chip_detect_sys_frequency()
94 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca955x_chip_detect_sys_frequency()
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
106 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca955x_chip_detect_sys_frequency()
243 uint32_t pll; in qca955x_chip_get_eth_pll() local
247 pll = QCA955X_PLL_VAL_10; in qca955x_chip_get_eth_pll()
250 pll = QCA955X_PLL_VAL_100; in qca955x_chip_get_eth_pll()
253 pll = QCA955X_PLL_VAL_1000; in qca955x_chip_get_eth_pll()
257 pll = 0; in qca955x_chip_get_eth_pll()
[all …]
H A Dqca953x_chip.c86 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
91 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca953x_chip_detect_sys_frequency()
93 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca953x_chip_detect_sys_frequency()
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
105 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca953x_chip_detect_sys_frequency()
236 uint32_t pll; in qca953x_chip_get_eth_pll() local
240 pll = QCA953X_PLL_VAL_10; in qca953x_chip_get_eth_pll()
243 pll = QCA953X_PLL_VAL_100; in qca953x_chip_get_eth_pll()
246 pll = QCA953X_PLL_VAL_1000; in qca953x_chip_get_eth_pll()
250 pll = 0; in qca953x_chip_get_eth_pll()
[all …]
H A Dar71xx_chip.c94 uint32_t pll; in ar71xx_chip_detect_sys_frequency() local
100 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_chip_detect_sys_frequency()
235 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar71xx_chip_set_pll_ge() argument
241 AR71XX_PLL_ETH_INT0_CLK, pll, in ar71xx_chip_set_pll_ge()
246 AR71XX_PLL_ETH_INT1_CLK, pll, in ar71xx_chip_set_pll_ge()
282 uint32_t pll; in ar71xx_chip_get_eth_pll() local
286 pll = PLL_ETH_INT_CLK_10; in ar71xx_chip_get_eth_pll()
289 pll = PLL_ETH_INT_CLK_100; in ar71xx_chip_get_eth_pll()
292 pll = PLL_ETH_INT_CLK_1000; in ar71xx_chip_get_eth_pll()
296 pll = 0; in ar71xx_chip_get_eth_pll()
[all …]
H A Dar724x_chip.c72 uint32_t pll; in ar724x_chip_detect_sys_frequency() local
78 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); in ar724x_chip_detect_sys_frequency()
80 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); in ar724x_chip_detect_sys_frequency()
83 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_chip_detect_sys_frequency()
88 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; in ar724x_chip_detect_sys_frequency()
91 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; in ar724x_chip_detect_sys_frequency()
146 ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar724x_chip_set_pll_ge() argument
H A Dar933x_chip.c178 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar933x_chip_set_pll_ge() argument
221 uint32_t pll; in ar933x_chip_get_eth_pll() local
225 pll = AR933X_PLL_VAL_10; in ar933x_chip_get_eth_pll()
228 pll = AR933X_PLL_VAL_100; in ar933x_chip_get_eth_pll()
231 pll = AR933X_PLL_VAL_1000; in ar933x_chip_get_eth_pll()
235 pll = 0; in ar933x_chip_get_eth_pll()
237 return (pll); in ar933x_chip_get_eth_pll()
/f-stack/freebsd/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/clock/
H A Dqca,ath79-pll.txt6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
H A Dkeystone-pll.txt15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
17 - reg - pll control0 and pll multipler registers
26 compatible = "ti,keystone,main-pll-clock";
35 compatible = "ti,keystone,pll-clock";
37 clock-output-names = "pa-pll-clk";
44 - compatible : shall be "ti,keystone,pll-mux-clock"
46 - reg - pll mux register
56 compatible = "ti,keystone,pll-mux-clock";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
68 - reg - pll mux register
[all …]
H A Dsnps,hsdk-pll-clock.txt8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
24 compatible = "snps,hsdk-core-pll-clock";
H A Dsilabs,si5351.txt30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
83 silabs,pll-source = <0 0>, <1 0>;
98 silabs,pll-master;
114 pll-master;
H A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
H A Dti-keystone-pllctrl.txt1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@02310000 {
H A Dqoriq-clock.txt87 4 platform pll n=pll/(n+1). For example, when n=1,
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
124 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
162 compatible = "fsl,qoriq-core-pll-1.0";
170 compatible = "fsl,qoriq-core-pll-1.0";
193 platform-pll: platform-pll@c00 {
196 compatible = "fsl,qoriq-platform-pll-1.0";
[all …]
H A Dsnps,pll-clock.txt8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
24 compatible = "snps,axs10x-arc-pll-clock";
H A Dclock-bindings.txt104 pll: pll@4c000 {
105 compatible = "vendor,some-pll-interface"
110 clock-output-names = "pll", "pll-switched";
120 clocks = <&osc 0>, <&pll 1>;
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
153 clocks = <&osc 0>, <&pll 1>;
156 assigned-clocks = <&clkcon 0>, <&pll 2>;
157 assigned-clock-parents = <&pll 2>;
161 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/sound/
H A Dpcm512x.txt20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
50 pll-in = <3>;
51 pll-out = <6>;
/f-stack/freebsd/contrib/device-tree/src/mips/qca/
H A Dar9132.dtsi17 clocks = <&pll ATH79_CLK_CPU>;
64 clocks = <&pll ATH79_CLK_AHB>;
89 pll: pll-controller@18050000 { label
90 compatible = "qca,ar9132-pll",
91 "qca,ar9130-pll";
107 clocks = <&pll ATH79_CLK_AHB>;
151 clocks = <&pll ATH79_CLK_AHB>;
H A Dar9331.dtsi17 clocks = <&pll ATH79_CLK_CPU>;
90 pll: pll-controller@18050000 { label
91 compatible = "qca,ar9330-pll";
126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
279 clocks = <&pll ATH79_CLK_AHB>;
/f-stack/freebsd/contrib/device-tree/src/c6x/
H A Dtms320c6457.dtsi62 compatible = "ti,c6457-pll", "ti,c64x+pll";
64 ti,c64x+pll-bypass-delay = <300>;
65 ti,c64x+pll-reset-delay = <24000>;
66 ti,c64x+pll-lock-delay = <50000>;
H A Dtms320c6474.dtsi83 compatible = "ti,c6474-pll", "ti,c64x+pll";
85 ti,c64x+pll-bypass-delay = <120>;
86 ti,c64x+pll-reset-delay = <30000>;
87 ti,c64x+pll-lock-delay = <60000>;
H A Dtms320c6455.dtsi72 compatible = "ti,c6455-pll", "ti,c64x+pll";
74 ti,c64x+pll-bypass-delay = <1440>;
75 ti,c64x+pll-reset-delay = <15360>;
76 ti,c64x+pll-lock-delay = <24000>;
/f-stack/freebsd/contrib/device-tree/Bindings/usb/
H A Dnvidia,tegra124-xusb.txt49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
53 - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
62 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
127 avdd-pll-utmip-supply = <&vddio_1v8>;
128 avdd-pll-erefe-supply = <&avdd_1v05_run>;
129 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/display/ti/
H A Dti,omap5-dss.txt64 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
65 - reg-names: "proto", "phy", "pll"
69 - clocks: handles to fclk and pll clock
86 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
88 - reg-names: "wp", "pll", "phy", "core"
92 - clocks: handles to fclk and pll clock

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